PIC18F67J11T-I Datasheet, PDF (100/466 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Flash Microcontrollers

PIC18F87J11 FAMILY
7.4 Erasing Flash Program Memory
The minimum erase block is 512 words or 1024 bytes.
Only through the use of an external programmer, or
through ICSP control, can larger blocks of program
memory be bulk erased. Word erase in the Flash array
is not supported.
When initiating an erase sequence from the micro-
controller itself, a block of 1024 bytes of program
memory is erased. The Most Significant 12 bits of the
TBLPTR<21:10> point to the block being erased.
TBLPTR<9:0> are ignored.
The EECON1 register commands the erase operation.
The WREN bit must be set to enable write operations.
The FREE bit is set to select an erase operation. For
protection, the write initiate sequence for EECON2
must be used.
A long write is necessary for erasing the internal Flash.
Instruction execution is halted while in a long write
cycle. The long write will be terminated by the internal
programming timer.
7.4.1
FLASH PROGRAM MEMORY
ERASE SEQUENCE
The sequence of events for erasing a block of internal
program memory location is:
1. Load Table Pointer register with address of row
being erased.
2. Set the WREN and FREE bits (EECON1<2,4>)
to enable the erase operation.
3. Disable interrupts.
4. Write H'55' to EECON2.
5. Write H'AA' to EECON2.
6. Set the WR bit. This will begin the row erase
cycle.
7. The CPU will stall for duration of the erase for
TIW (see Parameter D133A).
8. Re-enable interrupts.
EXAMPLE 7-2: ERASING A FLASH PROGRAM MEMORY ROW
ERASE_ROW
Required
Sequence
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
EECON1, WREN
EECON1, FREE
INTCON, GIE
H'55'
EECON2
H'AA'
EECON2
EECON1, WR
INTCON, GIE
; load TBLPTR with the base
; address of the memory block
; enable write to memory
; enable Row Erase operation
; disable interrupts
; write H'55'
; write H'AA'
; start erase (CPU stall)
; re-enable interrupts
DS39778E-page 100
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