PIC18F67J11T-I Datasheet, PDF (171/466 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Flash Microcontrollers

PIC18F87J11 FAMILY
REGISTER 12-4: PMMODEL: PARALLEL PORT MODE LOW BYTE REGISTER
R/W-0
WAITB1⁽¹⁾
bit 7
R/W-0
WAITB0⁽¹⁾
R/W-0
WAITM3
R/W-0
WAITM2
R/W-0
WAITM1
R/W-0
WAITM0
R/W-0
WAITE1⁽¹⁾
R/W-0
WAITE0⁽¹⁾
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
bit 5-2
bit 1-0
WAITB<1:0>: Data Setup to Read/Write Wait State Configuration bits⁽¹⁾
11 = Data wait of 4 TCY; multiplexed address phase of 4 TCY
10 = Data wait of 3 TCY; multiplexed address phase of 3 TCY
01 = Data wait of 2 TCY; multiplexed address phase of 2 TCY
00 = Data wait of 1 TCY; multiplexed address phase of 1 TCY
WAITM<3:0>: Read to Byte Enable Strobe Wait State Configuration bits
1111 = Wait of additional 15 TCY
...
0001 = Wait of additional 1 TCY
0000 = No additional Wait cycles (operation forced into one TCY)
WAITE1:WAITE0: Data Hold After Strobe Wait State Configuration bits⁽¹⁾
11 = Wait of 4 TCY
10 = Wait of 3 TCY
01 = Wait of 2 TCY
00 = Wait of 1 TCY
Note 1: WAITB and WAITE bits are ignored whenever WAITM<3:0> = 0000.
REGISTER 12-5: PMEH: PARALLEL PORT ENABLE HIGH BYTE REGISTER
R/W-0
PTEN15
bit 7
R/W-0
PTEN14
R/W-0
PTEN13
R/W-0
PTEN12
R/W-0
PTEN11
R/W-0
PTEN10
R/W-0
PTEN9
R/W-0
PTEN8
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
bit 5-0
PTEN<15:14>: PMCSx Strobe Enable bits
1 = PMA15 and PMA14 function as either PMA<15:14> or PMCS2 and PMCS1
0 = PMA15 and PMA14 function as port I/O
PTEN<13:8>: PMP Address Port Enable bits
1 = PMA<13:8> function as PMP address lines
0 = PMA<13:8> function as port I/O
 2007-2012 Microchip Technology Inc.
DS39778E-page 171