PIC18F67J11T-I Datasheet, PDF (65/466 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Flash Microcontrollers

PIC18F87J11 FAMILY
TABLE 5-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS⁽⁴⁾ (CONTINUED)
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets,
CM Resets
Wake-up via WDT
or Interrupt
PORTJ
PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTH
PIC18F6XJ1X PIC18F8XJ1X 0000 xxxx
uuuu uuuu
uuuu uuuu
PORTG
PIC18F6XJ1X PIC18F8XJ1X 000x xxxx
000u uuuu
uuuu uuuu
PORTF
PIC18F6XJ1X PIC18F8XJ1X x001 100-
xuuu uuu-
xuuu uuu-
PORTE
PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTD
PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTC
PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTB
PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTA
PIC18F6XJ1X PIC18F8XJ1X 000x 0000
000u 0000
uuuu uuuu
SPBRGH1 PIC18F6XJ1X PIC18F8XJ1X 0000 0000
0000 0000
uuuu uuuu
BAUDCON1 PIC18F6XJ1X PIC18F8XJ1X 0100 0-00
0100 0-00
uuuu u-uu
SPBRGH2 PIC18F6XJ1X PIC18F8XJ1X 0000 0000
0000 0000
uuuu uuuu
BAUDCON2 PIC18F6XJ1X PIC18F8XJ1X 0100 0-00
0100 0-00
uuuu u-uu
TMR3H
PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR3L
PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx
uuuu uuuu
uuuu uuuu
T3CON
PIC18F6XJ1X PIC18F8XJ1X 0000 0000
uuuu uuuu
uuuu uuuu
TMR4
PIC18F6XJ1X PIC18F8XJ1X 0000 0000
0000 0000
uuuu uuuu
PR4
PIC18F6XJ1X PIC18F8XJ1X 1111 1111
1111 1111
1111 1111
CVRCON
PIC18F6XJ1X PIC18F8XJ1X 0000 0000
0000 0000
uuuu uuuu
T4CON
PIC18F6XJ1X PIC18F8XJ1X -000 0000
-000 0000
-uuu uuuu
CCPR4H
PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR4L
PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP4CON PIC18F6XJ1X PIC18F8XJ1X --00 0000
--00 0000
--uu uuuu
CCPR5H
PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR5L
PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP5CON PIC18F6XJ1X PIC18F8XJ1X --00 0000
--00 0000
--uu uuuu
SSP2BUF
PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx
uuuu uuuu
uuuu uuuu
SSP2ADD
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
SSP2MSK
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
SSP2STAT PIC18F6XJ1X PIC18F8XJ1X 0000 0000
0000 0000
uuuu uuuu
SSP2CON1 PIC18F6XJ1X PIC18F8XJ1X 0000 0000
0000 0000
uuuu uuuu
SSP2CON2 PIC18F6XJ1X PIC18F8XJ1X 0000 0000
0000 0000
uuuu uuuu
CMSTAT
PIC18F6XJ1X PIC18F8XJ1X ---- --11
---- --11
---- --uu
Legend: u = unchanged; x = unknown; - = unimplemented bit, read as ‘0’; q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be effected (to cause wake-up).
4: See Table 5-2 for Reset value for specific conditions.
 2007-2012 Microchip Technology Inc.
DS39778E-page 65