PIC18F67J11T-I Datasheet, PDF (12/466 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Flash Microcontrollers

PIC18F87J11 FAMILY
TABLE 1-3: PIC18F6XJ1X PINOUT I/O DESCRIPTIONS
Pin Name
Pin Number _{Pin Buffer}
64-TQFP ^{Type Type}
Description
MCLR
7
I
ST Master Clear (Reset) input. This pin is an active-low Reset
to the device.
OSC1/CLKI/RA7
OSC1
CLKI
RA7
39
Oscillator crystal or external clock input. Available only in
External Oscillator modes (EC/ECPLL and HS/HSPLL).
I
ST Main oscillator input connection.
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode; CMOS
otherwise.
I CMOS Main clock input connection.
External clock source input. Always associated
with pin function, OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
I/O TTL General purpose I/O pin. Available only in INTIO2 and
INTPLL2 Oscillator modes.
OSC2/CLKO/RA6
OSC2
CLKO
RA6
40
Oscillator crystal or clock output. Available only in External
Oscillator modes (EC/ECPLL and HS/HSPLL).
O
— Main oscillator feedback output connection.
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
O
— System cycle clock output (FOSC/4).
In EC, ECPLL, INTIO1 and INTPLL1 Oscillator modes,
OSC2 pin outputs CLKO which has 1/4 the frequency
of OSC1 and denotes the instruction cycle rate.
I/O TTL General purpose I/O pin. Available only in INTIO1 and
INTPLL1 Oscillator modes.
Legend:
Note 1:
2:
TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I = Input
O
= Output
P = Power
I²C = ST with I²C™ or SMB levels
OD
= Open-Drain (no P diode to VDD)
Default assignment for ECCP2/P2A when Configuration bit, CCP2MX, is set.
Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared.
DS39778E-page 12
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