PIC18F67J11T-I Datasheet, PDF(79/466 Page) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Flash Microcontrollers

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PIC18F67J11T-I Datasheet, PDF (79/466 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Flash Microcontrollers

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PIC18F87J11 FAMILY

6.3.4 SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are registers used

by the CPU and peripheral modules for controlling the

desired operation of the device. These registers are

implemented as static RAM. SFRs start at the top of data

memory (FFFh) and extend downward to occupy more

than the top half of Bank 15 (F5Ah to FFFh). A list of these

registers is given inTable 6-3, Table 6-4 and Table 6-5.

The SFRs can be classified into two sets: those

associated with the âcoreâ device functionality (ALU,

Resets and interrupts) and those related to the

peripheral functions. The Reset and Interrupt registers

are described in their respective chapters, while the

ALUâs STATUS register is described later in this

section. Registers related to the operation of the

peripheral features are described in the chapter for that

peripheral.

The SFRs are typically distributed among the

peripherals whose functions they control. Unused SFR

locations are unimplemented and read as â0âs

Note:

Addresses, F5Ah through F5Fh, are not

part of the Access Bank. These registers

must always be accessed using the Bank

Select Register. Addresses, F40h to

F59h, are not implemented and are not

accessible to the user.

TABLE 6-3: SPECIAL FUNCTION REGISTER MAP FOR PIC18F87J11 FAMILY DEVICES

Address

Name

Address

Name

Address Name Address

FFFh

FFEh

FFDh

FFCh

FFBh

TOSU

TOSH

TOSL

STKPTR

PCLATU

FDFh INDF2(1)

FDEh POSTINC2(1)

FDDh POSTDEC2(1)

FDCh PREINC2(1)

FDBh PLUSW2(1)

FBFh ECCP1AS

FBEh ECCP1DEL

FBDh CCPR1H

FBCh CCPR1L

FBBh CCP1CON

F9Fh

F9Eh

F9Dh

F9Ch

F9Bh

FFAh

FF9h

PCLATH

PCL

FDAh

FD9h

FSR2H

FSR2L

FBAh ECCP2AS

FB9h ECCP2DEL

F9Ah

F99h

FF8h

FF7h

TBLPTRU

TBLPTRH

FD8h

FD7h

STATUS

TMR0H

FB8h CCPR2H

FB7h CCPR2L

F98h

F97h

FF6h

FF5h

TBLPTRL

TABLAT

FD6h

FD5h

TMR0L

T0CON

FB6h CCP2CON

FB5h ECCP3AS

F96h

F95h

FF4h PRODH

FF3h PRODL

FF2h INTCON

FF1h INTCON2

FF0h INTCON3

FEFh INDF0(1)

FEEh POSTINC0(1)

FEDh POSTDEC0(1)

FECh PREINC0(1)

FEBh PLUSW0(1)

FEAh FSR0H

FE9h FSR0L

FE8h WREG

FE7h INDF1(1)

FE6h POSTINC1(1)

FE5h POSTDEC1(1)

FE4h PREINC1(1)

FE3h PLUSW1(1)

FE2h FSR1H

FE1h FSR1L

FE0h

BSR

FD4h

FD3h

FD2h

FD1h

FD0h

FCFh

FCEh

FCDh

FCCh

FCBh

FCAh

FC9h

FC8h

FC7h

FC6h

FC5h

FC4h

FC3h

FC2h

FC1h

FC0h

â

OSCCON(3)

CM1CON

CM2CON

RCON

TMR1H(3)

TMR1L(3)

T1CON(3)

TMR2(3)

PR2(3)

T2CON

SSP1BUF

SSP1ADD

SSP1STAT

SSP1CON1

SSP1CON2

ADRESH

ADRESL

ADCON0(3)

ADCON1(3)

WDTCON

FB4h ECCP3DEL

FB3h CCPR3H

FB2h CCPR3L

FB1h CCP3CON

FB0h SPBRG1

FAFh RCREG1

FAEh TXREG1

FADh TXSTA1

FACh RCSTA1

FABh SPBRG2

FAAh RCREG2

FA9h TXREG2

FA8h TXSTA2

FA7h EECON2

FA6h EECON1

FA5h IPR3

FA4h PIR3

FA3h PIE3

FA2h IPR2

FA1h PIR2

FA0h PIE2

F94h

F93h

F92h

F91h

F90h

F8Fh

F8Eh

F8Dh

F8Ch

F8Bh

F8Ah

F89h

F88h

F87h

F86h

F85h

F84h

F83h

F82h

F81h

F80h

Name

IPR1

PIR1

PIE1

RCSTA2

OSCTUNE

TRISJ(2)

TRISH(2)

TRISG

TRISF

TRISE

TRISD

TRISC

TRISB

TRISA

LATJ(2)

LATH(2)

LATG

LATF

LATE

LATD

LATC

LATB

LATA

PORTJ(2)

PORTH(2)

PORTG

PORTF

PORTE

PORTD

PORTC

PORTB

PORTA

Address

Name

Address

F7Fh

F7Eh

F7Dh

F7Ch

F7Bh

SPBRGH1

BAUDCON1

SPBRGH2

BAUDCON2

TMR3H

F5Fh

F5Eh

F5Dh

F5Ch

F5Bh

F7Ah

F79h

TMR3L

T3CON

F5Ah

F59h

F78h

F77h

TMR4

PR4(3)

F58h

F57h

F76h

F75h

T4CON

CCPR4H

F56h

F55h

F74h

F73h

F72h

F71h

F70h

F6Fh

F6Eh

F6Dh

F6Ch

F6Bh

F6Ah

F69h

F68h

F67h

F66h

F65h

F64h

CCPR4L

CCP4CON

CCPR5H

CCPR5L

CCP5CON

SSP2BUF

SSP2ADD

SSP2STAT

SSP2CON1

SSP2CON2

CMSTAT

PMADDRH(4)

PMADDRL(4)

PMDIN1H

PMDIN1L

PMCONH

PMCONL

F54h

F53h

F52h

F51h

F50h

F4Fh

F4Eh

F4Dh

F4Ch

F4Bh

F4Ah

F49h

F48h

F47h

F46h

F45h

F44h

F63h PMMODEH

F62h PMMODEL

F43h

F42h

F61h PMDOUT2H

F60h PMDOUT2L

F41h

F40h

Name

PMDIN2H

PMDIN2L

PMEH

PMEL

PMSTATH

PMSTATL

â

â

â

â

â

â

â

â

â

â

â

â

â

â

â

â

â

â

â

â

â

â

â

â

â

â

Note 1: This is not a physical register.

2: This register is not available on 64-pin devices.

3: This register shares the same address with another register (see Table 6-4 for alternate register).

4: The PMADDRH/L and PMDOUT1H/L register pairs share the same address. PMADDR is used in Master modes and PMDOUT1 is used in

Slave modes.

5: Addresses, F40 to F59, are not implemented and are not accessible to the user.

ï£ 2007-2012 Microchip Technology Inc.

DS39778E-page 79

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