PIC18F67J11T-I Datasheet, PDF (162/466 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Flash Microcontrollers

PIC18F87J11 FAMILY
TABLE 11-18: PORTH FUNCTIONS
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
Description
RH0/A16
RH0
0
O DIG LATH<0> data output.
1
I
ST PORTH<0> data input.
A16
x
O DIG External Memory Interface, Address Line 16. Takes priority over port data.
RH1/A17
RH1
0
O DIG LATH<1> data output.
1
I
ST PORTH<1> data input.
A17
x
O DIG External Memory Interface, Address Line 17. Takes priority over port data.
RH2/A18/
PMD7
RH2
0
O DIG LATH<2> data output.
1
I
ST PORTH<2> data input.
A18
x
O DIG External Memory Interface, Address Line 18. Takes priority over port data.
PMD7⁽²⁾
x
O DIG Parallel Master Port data out.
x
I
TTL Parallel Master Port data input.
RH3/A19/
PMD6
RH3
0
O DIG LATH<3> data output.
1
I
ST PORTH<3> data input.
A19
x
O DIG External Memory Interface, Address Line 19. Takes priority over port data.
PMD6⁽²⁾
x
O DIG Parallel Master Port data out.
x
I
TTL Parallel Master Port data input.
RH4/PMD3/
AN12/P3C/
C2INC
RH4
0
1
PMD3⁽²⁾
x
O DIG LATH<4> data output.
I
ST PORTH<4> data input.
I
TTL Parallel Master Port data out.
x
O DIG Parallel Master Port data input.
AN12
I ANA A/D Input Channel 12. Default input configuration on POR; does not affect
digital output.
P3C⁽¹⁾
0
O DIG ECCP3 Enhanced PWM output, Channel C; takes priority over port and PMP
data. May be configured for tri-state during Enhanced PWM shutdown events.
C2INC
x
I ANA Comparator 2 Input C.
RH5/PMBE/
AN13/P3B/
C2IND
RH5
0
1
PMBE⁽²⁾
x
O DIG LATH<5> data output.
I
ST PORTH<5> data input.
O DIG Parallel Master Port data byte enable.
AN13
I ANA A/D Input Channel 13. Default input configuration on POR; does not affect
digital output.
P3B⁽¹⁾
0
O DIG ECCP3 Enhanced PWM output, Channel B; takes priority over port and PMP
data. May be configured for tri-state during Enhanced PWM shutdown events.
C2IND
x
I ANA Comparator 2 Input D.
RH6/PMRD/
RH6
0
AN14/P1C/
C1INC
1
PMRD⁽²⁾
x
O DIG LATH<6> data output.
I
ST PORTH<6> data input.
O DIG Parallel Master Port read strobe.
x
I
TTL Parallel Master Port read in.
AN14
I ANA A/D Input Channel 14. Default input configuration on POR; does not affect
digital output.
P1C⁽¹⁾
0
O DIG ECCP1 Enhanced PWM output, Channel C; takes priority over port and PMP
data. May be configured for tri-state during Enhanced PWM shutdown events.
C1INC
x
I ANA Comparator 1 Input C.
Legend:
Note 1:
2:
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Alternate assignments for P1B/P1C and P3B/P3C when the ECCPMX Configuration bit is cleared. Default assignments
are PORTE<6:3>.
Alternate PMP configuration when the PMPMX Configuration bit = 0; available on 80-pin devices only.
DS39778E-page 162
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