PIC18F67J11T-I Datasheet, PDF (221/466 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Flash Microcontrollers

PIC18F87J11 FAMILY
19.1.3
USE OF CCP4 AND CCP5 WITH
ECCP1 AND ECCP3
Only the ECCP2 module has four dedicated output pins
that are available for use. Assuming that the I/O ports
or other multiplexed functions on those pins are not
needed, they may be used whenever needed without
interfering with any other CCP module.
ECCP1 and ECCP3, on the other hand, only have
three dedicated output pins: ECCPx/PxA, PxB and
PxC. Whenever these modules are configured for
Quad PWM mode, the pin normally used for CCP4 or
CCP5 becomes the PxD output pin for ECCP3 and
ECCP1, respectively. The CCP4 and CCP5 modules
remain functional but their outputs are overridden.
19.1.4
ECCP MODULES AND TIMER
RESOURCES
Like the standard CCP modules, the ECCP modules
can utilize Timers 1, 2, 3 or 4, depending on the mode
selected. Timer1 and Timer3 are available for modules
in Capture or Compare modes, while Timer2 and
Timer4 are available for modules in PWM mode.
Additional details on timer resources are provided in
Section 18.1.1 “CCP Modules and Timer
Resources”.
19.1.5 OPEN-DRAIN OUTPUT OPTION
When operating in compare or standard PWM modes,
the drivers for the ECCP pins can be optionally
configured as open-drain outputs. This feature allows
the voltage level on the pin to be pulled to a higher level
through an external pull-up resistor, and allows the
output to communicate with external circuits without the
need for additional level shifters. For more information,
see Section 11.1.5 “Open-Drain Outputs”
The open-drain output option is controlled by the bits in
the ODCON1 register. Setting the appropriate bit
configures the pin for the corresponding module for
open-drain operation. The ODCON1 memory shares
the same address space as of TMR1H. The ODCON1
register can be accessed by setting the ADSHR bit in
the WDTCON register (WDTCON<4>).
TABLE 19-1: PIN CONFIGURATIONS FOR ECCP1
ECCP Mode
CCP1CON
Configuration
RC2
RE6
RE5
RG4
RH7
RH6
All PIC18F6XJ1X Devices:
Compatible CCP 00xx 11xx ECCP1
RE6
RE5
RG4/CCP5
N/A
N/A
Dual PWM
10xx 11xx
P1A
P1B
RE5
RG4/CCP5
N/A
N/A
Quad PWM⁽¹⁾
x1xx 11xx
P1A
P1B
P1C
P1D
N/A
N/A
PIC18F8XJ1X Devices, ECCPMX = 0, Microcontroller mode:
Compatible CCP
Dual PWM
Quad PWM⁽¹⁾
00xx 11xx
10xx 11xx
x1xx 11xx
ECCP1
P1A
P1A
RE6/AD14
RE6/AD14
RE6/AD14
RE5/AD13
RE5/AD13
RE5/AD13
RG4/CCP5
RG4/CCP5
P1D
RH7/AN15
P1B
P1B
RH6/AN14
RH6/AN14
P1C
PIC18F8XJ1X Devices, ECCPMX = 1, Extended Microcontroller mode, 16-Bit or 20-Bit Address Width:
Compatible CCP 00xx 11xx ECCP1 RE6/AD14 RE5/AD13 RG4/CCP5 RH7/AN15 RH6/AN14
PIC18F8XJ1X Devices, ECCPMX = 1,
Microcontroller mode or Extended Microcontroller mode, 12-Bit Address Width:
Compatible CCP 00xx 11xx ECCP1 RE6/AD14 RE5/AD13 RG4/CCP5 RH7/AN15 RH6/AN14
Dual PWM
10xx 11xx
P1A
P1B
RE5/AD13 RG4/CCP5 RH7/AN15 RH6/AN14
Quad PWM⁽¹⁾
x1xx 11xx
P1A
P1B
P1C
P1D
RH7/AN15 RH6/AN14
Legend: x = Don’t care, N/A = Not Available. Shaded cells indicate pin assignments not used by ECCP1 in a given mode.
Note 1: With ECCP1 in Quad PWM mode, the CCP5 module’s output is overridden by P1D; otherwise, CCP5 is fully
operational.
 2007-2012 Microchip Technology Inc.
DS39778E-page 221