PIC18F67J11T-I Datasheet, PDF (244/466 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Flash Microcontrollers

PIC18F87J11 FAMILY
20.3.7 SLAVE MODE
In Slave mode, the data is transmitted and received as
the external clock pulses appear on SCKx. When the
last bit is latched, the SSPxIF interrupt flag bit is set.
While in Slave mode, the external clock is supplied by
the external clock source on the SCKx pin. This exter-
nal clock must meet the minimum high and low times
as specified in the electrical specifications.
While in Sleep mode, the slave can transmit/receive
data. When a byte is received, the device can be
configured to wake-up from Sleep.
20.3.8
SLAVE SELECT
SYNCHRONIZATION
The SSx pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with the SSx pin control
enabled (SSPxCON1<3:0> = 04h). When the SSx pin
is low, transmission and reception are enabled and the
SDOx pin is driven. When the SSx pin goes high, the
SDOx pin is no longer driven, even if in the middle of a
transmitted byte and becomes a floating output. Exter-
nal pull-up/pull-down resistors may be desirable
depending on the application.
Note 1: When the SPI is in Slave mode, with
the SSx pin control enabled,
(SSPxCON1<3:0> = 0100), the SPI
module will reset if the SSx pin is set to
VDD.
2: If the SPI is used in Slave mode, with CKE
set, then the SSx pin control must be
enabled.
When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SSx pin to
a high level or clearing the SSPEN bit.
To emulate two-wire communication, the SDOx pin can
be connected to the SDIx pin. When the SPI needs to
operate as a receiver, the SDOx pin can be configured
as an input; this disables transmissions from the SDOx.
The SDIx can always be left as an input (SDI function)
since it cannot create a bus conflict.
FIGURE 20-4:
SLAVE SYNCHRONIZATION WAVEFORM
SSx
SCKx
(CKP = 0
CKE = 0)
SCKx
(CKP = 1
CKE = 0)
Write to
SSPxBUF
SDOx
SDIx
(SMP = 0)
Input
Sample
(SMP = 0)
SSPxIF
Interrupt
Flag
SSPxSR to
SSPxBUF
bit 7
bit 6
bit 7
bit 7
bit 7
bit 0
bit 0
Next Q4 Cycle
After Q2
DS39778E-page 244
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