PIC18F67J11T-I Datasheet, PDF (418/466 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Flash Microcontrollers

PIC18F87J11 FAMILY
28.4.3 TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 28-4:
EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
OSC1
CLKO
1
3
3
2
Q4
Q1
4
4
TABLE 28-6: EXTERNAL CLOCK TIMING REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Max Units
Conditions
1A
FOSC
External CLKI Frequency⁽¹⁾
DC
48
MHz EC Oscillator mode
DC
10
ECPLL Oscillator mode
Oscillator Frequency⁽¹⁾
4
25
MHz HS Oscillator mode
4
10
HSPLL Oscillator mode
1
TOSC
External CLKI Period⁽¹⁾
20.8
—
ns _{EC Oscillator mode}
100
—
ECPLL Oscillator mode
Oscillator Period⁽¹⁾
40.0
250
ns HS Oscillator mode
100
250
HSPLL Oscillator mode
2
TCY
Instruction Cycle Time⁽¹⁾
83.3
—
ns TCY = 4/FOSC, Industrial
3
TOSL,
External Clock in (OSC1)
10
TOSH
High or Low Time
—
ns HS Oscillator mode
4
TOSR, External Clock in (OSC1)
—
TOSF
Rise or Fall Time
7.5
ns HS Oscillator mode
Note 1:
Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations
except PLL. All specified values are based on characterization data for that particular oscillator type under
standard operating conditions with the device executing code. Exceeding these specified limits may result
in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested
to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock
input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
DS39778E-page 418
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