LTC3882_15 Datasheet, PDF (8/104 Pages) Linear Technology – Dual Output PolyPhase Step-Down DC/DC Voltage Mode Controller with Digital Power System Management

LTC3882
ELECTRICAL CHARACTERISTICS
Note 4: EEPROM endurance, retention and mass write times are
guaranteed by design, characterization and correlation with statistical
process controls. Minimum retention applies only for devices cycled less
than the minimum endurance specification. EEPROM read commands
(e.g. RESTORE_USER_ALL) are valid over the entire specified operating
junction temperature range.
Note 5: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to GND unless otherwise
specified.
Note 6: Minimum EEPROM endurance, retention and mass write time
specifications apply when writing data with 3.15V ≤ V_DD33 ≤ 3.45V.
EEPROM read commands are valid over the entire specified V_DD33
operating range.
Note 7: Specified V_OUT accuracy with AVP = 0% requires servo mode to
be set with MFR_PWM_MODE_LTC3882 command bit 6. Performance is
guaranteed by testing the LTC3882 in a feedback loop that servos V_OUT to
a specified value.
Note 8: ADC tested with PWMs disabled. Comparable capability
demonstrated by in-circuit evaluations. Total Unadjusted Error includes all
gain and linearity errors, as well as offsets.
Note 9: Internal 32-bit calculations using 16-bit ADC results are limited to
10-bit resolution by PMBus Linear 11-bit data format.
Note 10: Limits guaranteed by TSNS voltage and current measurements
during test, including ADC readback.
Note 11: Data conversion is done in round robin fashion. All inputs signals
are continuously scanned in sequence resulting in a typical conversion
latency of 100ms.
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Load Current
(1-Phase Using DS12S1R880A
Power Block)
95
V_IN = 12V
90
85
3.3V
80
2.5V
1.8V
1.5V
1.2V
1.0V
75
0
10
20
30
40
LOAD CURRENT (A)
3882 G01
Typical Distribution of Slave
I_OUT Offset (Not Including DCR
Mismatch)
4000
3500
3000
9595 UNITS
FROM 3 LOTS
T_A = –40°C
T_J = –22°C
CHO MASTER
2500
2000
1500
1000
500
0
–400–300–200–100 0 100 200 300 400
CH1 I_SENSE OFFSET TO IDEAL (µV)
3882 G25
8
Efficiency vs Load Current
(3-Phase Using DS12S1R845A
Power Block)
94
V_IN = 12V
92 ^{VOUT = 1.5V}
90
88
86
84
82
80
0 10 20 30 40 50 60 70
LOAD CURRENT (A)
3882 G02
Typical Distribution of Slave
I_OUT Offset (Not Including DCR
Mismatch)
3500
3000
2500
8593 UNITS
FROM 3 LOTS
T_J = 38°C
CHO MASTER
2000
1500
1000
500
0
–400–300–200–100 0 100 200 300 400
CH1 I_SENSE OFFSET TO IDEAL (µV)
3882 G25
Efficiency and Power Loss vs
Input Voltage
(1-Phase Using LTC4449)
100
3.0
V_O = 1.8V
98
96
2.5
94
2.0
92
90
1.5
88
86
1.0
84
82 ^{POWER FET: BSC050N04LS G}
SYNC FET: BSC010N04LS
80
5
10
15
20
V_IN (V)
0.5
0
25
30
3882 G03
Typical Distribution of Slave
I_OUT Offset (Not Including DCR
Mismatch)
4500
4000
3500
11783 UNITS
FROM 3 LOTS
T_J = 121°C
CHO MASTER
3000
2500
2000
1500
1000
500
0
–300–200–100 0 100 200 300 400 500
CH1 I_SENSE OFFSET TO IDEAL (µV)
3882 G26
3882f
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