LTC3882_15 Datasheet, PDF (26/104 Pages) Linear Technology – Dual Output PolyPhase Step-Down DC/DC Voltage Mode Controller with Digital Power System Management

LTC3882
OPERATION
Mapping Faults to GPIO Pins
The LTC3882 can map various fault indicators to their
respective GPIO pin using the MFR_GPIO_PROPAGATE_
LTC3882 command.
Channel-to-channel fault dependencies and communica-
tion can be created by connecting GPIO pins together. In
the event of an internal fault, one or more of the channels
is configured to pull the bussed GPIO pins low. All chan-
nels are then configured to shut down when the bussed
GPIO pins are pulled low (MFR_GPIO_RESPONSE set to
0xc0). If latch off is the programmed response on the
faulted channel, the GPIO pin remains low until one of
the following occurs:
• A CLEAR_FAULTS, RESTORE_USER_ALL or MFR_RE-
SET Command Is Issued
• The Related Status Bit Is Written to a One
• The Faulted Channel Is Properly Commanded Off and
Back On
• IC Supply Power Is Cycled
For autonomous group retry, the faulted channel is con-
figured to release the GPIO pin(s) after a retry interval,
assuming the original fault has cleared. All the channels
in the group then begin a soft-start sequence.
Other GPIO Uses
A GPIO pin can also find usage as a driver for an external
crowbar device, overtemperature alert, overvoltage alert,
or as an interrupt to cause a microcontroller to poll the
status commands. The GPIO pins may be configured as
inputs to detect faults external to the controller that require
an immediate response. External faults propagated into
the chip using GPIOn pins are not deglitched.
The GPIO pins can also serve as power good indicator
outputs. On master phases, this designates the controller’s
output is within the desired regulation limits. As described
in the previous Voltage-Based Output Sequencing section,
the GPIO pins also make it possible to control start-up
through concatenated events.
Refer to the MFR_GPIO_PROPAGATE command for ad-
ditional details.
Fault Logging
The LTC3882 has fault logging capability. During normal
operation log data is continuously updated in internal RAM.
When a fault occurs that disables either PWM controller,
recording to internal memory is halted, the fault log informa-
tion is made available from RAM via the MFR_FAULT_LOG
command, and the contents of the RAM log are copied
into EEPROM. EEPROM fault logging is allowed above
a die temperature of 85°C, but 10 years of retention is
not guaranteed. When die temperature exceeds 130°C
EEPROM fault logging is delayed until the temperature
drops below 125°C. Faults generating a log should be fully
cleared before the log is erased to prevent generation of
spurious fault logs. Faults propagated into the IC through
GPIOn pins do not trigger a fault logging event.
When the LTC3882 powers up it checks the EEPROM for
a valid fault log. If one is found the Valid Fault Log bit in
the STATUS_MFR_SPECIFIC PMBus command is set.
Additional fault logging will be disabled until the LTC3882
receives a CLEAR_FAULTS command. If the Memory Fault
Detected bit is also set in STATUS_CML, then the stored
fault log is partial. Data in one or more event records may
be incomplete or incorrect and MFR_CLEAR_FAULT_LOG
should also be commanded after all faults are cleared in
order to fully enable additional logging functions.
The MFR_FAULT_LOG command uses a block read protocol
with a fixed length of 147 bytes. The LTC3882 returns a
block byte count of zero if a fault log is not present.
Contents of a fault log are shown in Table 1 through Table 4.
Refer to Table 6 for an explanation of data formats. Each
event record represents one complete conversion cycle
through all multiplexed monitor ADC inputs and related
status. The six most recent event records are maintained
in internal memory in reverse chronological order. When
a fault log is created the present ADC input cycle is com-
pleted and the ADC input being converted at the time of
the fault is noted in the log header record.
3882f
26
For more information www.linear.com/LTC3882