LTC3882_15 Datasheet, PDF (12/104 Pages) Linear Technology – Dual Output PolyPhase Step-Down DC/DC Voltage Mode Controller with Digital Power System Management

LTC3882
PIN FUNCTIONS
ALERT (Pin 11): Open-Drain Status Output. This pin may
be connected to the system SMBALERT wire-AND inter-
rupt signal and should be left open if not used. If used,
a pull-up resistor to 3.3V is required in the application.
GPIO0/GPIO1 (Pin 12/Pin 13): Programmable General
Purpose Digital Inputs and Open-Drain Outputs. Uses
include status indication, external device control, and
channel-to-channel fault communication and propaga-
tion. These pins should be left open if not used. If used,
a pull-up resistor to 3.3V is required in the application.
RUN0/RUN1 (Pin 14/Pin 15): Run Control Inputs and
Open-Drain Outputs. A voltage above 2V is required on
these pins to enable the respective PWM channel. The
LTC3882 will drive these pins low under certain reset/restart
conditions regardless of any PMBus command settings.
A pull-up resistor to 3.3V is required in the application.
ASEL0/ASEL1 (Pin 16/Pin 17): Serial Bus Address Select
Inputs. Connect optional 1% resistor dividers between
V_DD25 and GND to these pins to select the serial bus
interface address. Refer to the Applications Information
section for more detail.
V_{OUT0_CFG}/V_{OUT1_CFG} (Pin 18/Pin 19): Output Voltage
Configuration Inputs. Connect optional 1% resistor divid-
ers between V_DD25 and GND to these pins to select the
output voltage for each channel. Refer to the Applications
Information section for more detail.
FREQ_CFG (Pin 20): Frequency Configuration Input. Con-
nect an optional 1% resistor divider between V_DD25 and GND
to this pin to configure PWM switching frequency. Refer
to the Applications Information section for more detail.
PHAS_CFG (Pin 21): Phase Configuration Input. Connect
an optional 1% resistor divider between V_DD25 and GND
to this pin to configure the phase of each PWM channel
relative to SYNC. Refer to the Applications Information
section for more detail.
V_DD25 (Pin 22): Internal 2.5V Regulator Output. Bypass
this pin to GND with a low ESR 1µF capacitor. Do not load
this pin with external current beyond that required for local
LTC3882 configuration pins, if any.
WP (Pin 23): Write Protect Input. If WP is above 2V, PMBus
writes are restricted and any software WRITE_PROTECT
settings are overridden. Refer to PMBus Command De-
tails for more information. This pin has an internal 10µA
pull-up to V_DD33.
SHARE_CLK (Pin 24): Share Clock Input and Open-Drain
Output. Share Clock, nominally 100kHz, is used to sequence
multiple rails in a power system utilizing more than one
LTC PSM controller. A pull-up resistor to 3.3V is required
in the application. Minimize the capacitance on this line to
ensure the time constant is fast enough for the application.
V_DD33 (Pin 25): Internal 3.3V Regulator Output. Bypass this
pin to GND with a low ESR 2.2µF capacitor. The LTC3882
may also be powered from an external 3.3V rail attached
to this pin, if also shorted to V_CC. Do not overload this
pin with external system current. Local pull-up resistors
for the LTC3882 itself may be powered from V_DD33. Refer
to the Applications Information section for more detail.
V_CC (Pin 26): 3.3V Regulator Input. Bypass this pin to
GND with a capacitor (0.1µF to 1µF ceramic) in close
proximity to the IC.
V_SENSE0– (Pin 35): Channel 0 Negative Output Voltage
Sense Input. This pin must still be properly connected
on slave channels for accurate output current telemetry.
V_SENSE0+/V_SENSE1+ (Pin 36/Pin 34): Positive Output Voltage
Sense Inputs. These pins must still be properly connected
on slave channels for accurate output current telemetry.
I_SENSE0–/I_SENSE1– (Pin 37/Pin 33): Current Sense Ampli-
fier Inputs. The (–) inputs to the amplifiers are normally
connected to the low side of a DCR sensing network or
output current sense resistor for each phase.
I_SENSE0+/I_SENSE1+ (Pin 38/Pin 32): Current Sense Ampli-
fier Inputs. The (+) inputs are normally connected to the
high side of an output current sense resistor or the R-C
midpoint of a parallel DCR sense circuit.
I_AVG0/I_AVG1 (Pin 39/Pin 31): Average Current Control Pins.
A capacitor connected between these pins and I_{AVG_GND}
stores a voltage proportional to the average output current
of the master channel. PolyPhase control is then imple-
3882f
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