LTC3882_15 Datasheet, PDF (15/104 Pages) Linear Technology – Dual Output PolyPhase Step-Down DC/DC Voltage Mode Controller with Digital Power System Management

LTC3882
OPERATION
• Operating Condition Telemetry
Main Control Loop
• Phase Locked Loop for Synchronous PolyPhase Opera-
tion (2, 3, 4, 6, or 8 phases)
• Fully Differential Load Sense
• Non-Volatile Configuration Memory
• Optional External Configuration Resistors for Key Op-
erating Parameters
• Optional Time-Base Interconnect for Synchronization
Between Multiple Controllers
• Fault Event Data Logging
• WP Pin to Protect Internal Configuration
• Capable of Standalone Operation with Default Factory
Configuration
• PMBus Revision 1.2 Compliant Interface up to 400kHz
The PMBus interface provides access to important power
management data during system operation including:
• Average Input Voltage
• Average Output Voltages
• Average Output Currents
• Average PWM Duty Cycles
• Internal LTC3882 Temperature
• External Sensed Temperatures
• Warning and Fault Status, Including Input and Output
Undervoltage and Overvoltage
The LTC3882 supports four serial bus addressing schemes
to access the individual PWM channels separately or jointly.
Fault reporting and system response behavior are fully
configurable. Two status outputs are provided (GPIO0,
GPIO1) that can be controlled independently. A separate
ALERT pin also provides for a maskable SMBALERT#.
Fault responses for each channel may be individually
programmed, depending on the fault type. PMBus status
commands allow fault reporting over the serial bus to
identify a specific fault event.
The LTC3882 utilizes constant frequency voltage mode con-
trol with leading-edge modulation. This provides improved
response to a load step increase, especially at larger V_IN/
V_OUT ratios found in the low voltage, high current solutions
demanded by modern digital subsystems. The LTC3882
leading-edge modulation architecture does not have a
minimum on-time requirement. Minimum duty cycle will
be determined by performance limits of the external power
stage. The IC is also capable of active voltage positioning
(AVP) to afford the smallest output capacitors possible for a
given output voltage accuracy over the anticipated full load
range. The LTC3882 error amplifiers have high bandwidth,
low offset and low output impedance, allowing the control
loop compensation network to be optimized for very high
crossover frequencies and excellent transient response.
The controller also achieves outstanding line transient
response by using input feedforward compensation to
instantaneously adjust PWM duty cycle and significantly
reduce output under/overshoot during supply voltage
changes. This also has the added advantage of making
the DC loop gain independent of input voltage.
The main PWM control loop used for each channel is
illustrated in Figure 1. During normal operation the top
MOSFET (power switch) driving choke L1 is commanded
off when the clock for that channel resets the RS latch.
The power switch is commanded back on when the main
PWM comparator VC, sets the RS latch. The error ampli-
fier EA output (COMP) controls the PWM duty cycle to
match the FB voltage to the EA positive terminal voltage
in steady state. A patented circuit adjusts this output for
VINSNS line feedforward.
The positive terminal of the EA is connected to the output
of a 12-bit DAC with values ranging from 0V to 1.024V.
The DAC value is determined by the resistor configuration
pins detailed in application Table 8, by values retrieved
from internal EEPROM, or by a combination of PMBus
commands to synthesize the desired output voltage. Refer
to the following PMBus Command Details section of this
document for more information. The LTC3882 supports
two output ranges. EA can regulate the output voltage to
5.5x the DAC output (Range 0) or 2.75x the DAC output
(Range 1).
For more information www.linear.com/LTC3882
3882f
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