LTC3882_15 Datasheet, PDF(46/104 Page) Linear Technology – Dual Output PolyPhase Step-Down DC/DC Voltage Mode Controller with Digital Power System Management

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LTC3882_15 Datasheet, PDF (46/104 Pages) Linear Technology – Dual Output PolyPhase Step-Down DC/DC Voltage Mode Controller with Digital Power System Management

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LTC3882

APPLICATIONS INFORMATION

Required error amplifier gain at frequency fC is:

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fLC

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15.56

Once the value of resistor R1 (function of selected VOUT

range) and pole/zero locations have been decided, the

value of R2, C1, C2, R3 and C3 can be obtained from the

previous equations.

Compensating a switching power supply feedback loop is

a complex task. The applications shown in this data sheet

provide typical values, optimized for the power components

shown. Though similar power components should suffice,

substantially changing even one major power component

may degrade performance significantly. Stability also may

depend on circuit board layout. To verify the calculated

component values, all new circuit designs should be

prototyped and tested for stability.

decoupling for the two channels, as a large resonant

loop can result. Vias should not be used to make these

connections. Avoid blocking forced air flow to the

switching FETs with large size passive components.

3. If using a discrete FET driver, place that IC close to the

switching FET gate terminals, keeping the connecting

traces short to produce clean drive signals. This rule

also applies to driver IC supply and ground pins that

connect to the switching FET source pins. The driver

IC can be placed on the opposite side of the PCB from

the switching FETs.

4. Place the inductor input as close as possible to the

switching FETs. Minimize the surface area of the switch

node. Make the trace width the minimum needed to

support the maximum output current. Avoid copper

fills or pours. Avoid running the connection on multiple

copper layers in parallel. Minimize capacitance from

the switch node to any other trace or plane.

PCB Layout Considerations

To prevent magnetic and electrical field radiation or high

frequency resonant problems and to ensure correct IC

operation, proper layout of the components connected to

the LTC3882 is essential. Refer to Figure 24, which also

illustrates current waveforms typically present in the circuit

branches. RSENSE will be replaced with a dead short if DCR

sensing is used. For maximum efficiency, the switch node

rise and fall times should be minimized. The following

PCB design priority list will help ensure proper topology.

1. Place a ground or DC voltage layer between a power

layer and a small-signal layer. Generally, power planes

should be placed on the top layer (4-layer PCB), or top

and bottom layer if more than 4 layers are used. Use

wide/short copper traces for power components and

avoid improper use of thermal relief around power

plane vias to minimize resistance and inductance.

2. Low ESR input capacitors should be placed as close

as possible to switching FET supply and ground con-

nections with the shortest copper traces possible. The

switching FETs must be on the same layer of copper

as the input capacitors with a common topside drain

connection at CIN. Do not attempt to split the input

5. Place the output current sense resistor (if used) im-

mediately adjacent to the inductor output. PCB traces

for remote voltage and current sense should be run

together back to the LTC3882 in pairs with the small-

est spacing possible on any given layer on which they

are routed. Avoid high frequency switching signals

and ideally shield with ground planes. Locate any

filter component on these traces next to the LTC3882,

and not at the Kelvin sense location. However, if DCR

sensing is used, place the top resistor (R1, Figure 25)

close to the switch node.

6. Place low ESR output capacitors adjacent to the sense

resistor output and ground. Output capacitor ground

connections must feed into the same copper that con-

nects to the input capacitor ground before connecting

back to system ground.

7. Connection of switching ground to system ground,

small-signal analog ground or any internal ground

plane should be single-point. If the system has an

internal system ground plane, a good way to do this

is to cluster vias into a single star point to make the

connection. This cluster should be located directly

beneath the IC GND paddle, which serves as both

analog signal ground and the negative sense for VOUT1.

3882f

For more information www.linear.com/LTC3882

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