LTC3882_15 Datasheet, PDF (54/104 Pages) Linear Technology – Dual Output PolyPhase Step-Down DC/DC Voltage Mode Controller with Digital Power System Management

LTC3882
APPLICATIONS INFORMATION
unless masked. The fault can be cleared by writing a 1 to
STATUS_MFR_SPECIFIC bit 4. A spurious ALERT for an
unlocked PLL may occur at start-up or during a reset if
this fault is not masked.
Neither PWM channel will transition from off to the RUN
state until PLL lock is indicated. When transitioning a
channel from off to RUN, bit 4 of STATUS_MFR_SPECIFIC
will be set if the PWM ramp generator for that channel
is not also locked to the desired PLL output frequency.
If the SYNC pin is not externally clocked in the application,
the PWMs will operate at the frequency specified by a non-
zero FREQUENCY_SWITCH command. If that command
is set to 0x0000 (external clock only) in EEPROM or with
RCONFIG (FREQ_CFG pin grounded), then at power-up,
or MFR_RESET, or RESTORE_USER_ALL, the PWM will
not start without an external clock input. If the external
clock is lost while programmed for external clock only, or
if the PWM is simply switched to this setting under power
with no external clock present, the PLL will start/run at
the lowest free running frequency created by the internal
VCO. This can be well below the intended PWM frequency
of the application and may cause undesirable operation of
the converter. For this reason, it is generally recommended
that a useable PWM frequency be programmed for each
channel, regardless of whether that particiular LTC3882
unit serves as clock master, or not.
All channels of a PolyPhase rail are required to share SYNC
pins. Between rails and for other configurations, such syn-
chronization is optional. If the SYNC pin is shared between
LTC3882s, only one LTC3882 should be programmed to
control the SYNC output.
PolyPhase Operation and Load Sharing
When the LTC3882 is used in a PolyPhase application, the
slave phases must be configured as such by connecting
their FB pins to V_DD33. Among other things, this disables
the error amplifiers of the slave phases. Five other pins
must then also be shared between all channels of a
PolyPhase rail:
• VINSNS
• COMP
• I_AVG
• I_{AVG_GND}
• SYNC
Using a common VINSNS connection reduces the dynamic
range required by the current loop and helps maintain
well-controlled master modulator gain.
The shared COMP signal allows the master phase error
amplifier to control the duty cycle of all slave phases to
produce the commanded output voltage.
Slave phases can detect system faults that cause the
master COMP (error amplifier) output to be too high. A
slave phase detecting this kind of error amplifier fault im-
mediately shuts off its PWM output, indicates the fault on
its VOUT_OV Fault bit, and takes whatever additional action
may be indicated by VOUT_OV_FAULT_RESPONSE for that
channel. If this response is set to only provide hardware-
level response (0x00), then normal channel operation will
automatically resume when the fault condition is cleared.
The shared I_AVG and I_{AVG_GND} signals actively balance the
amount of output current delivered from each channel using
a secondary current sharing loop. A capacitor with a value
between 100pF and 200pF should be placed between I_AVG
and I_{AVG_GND}. This capacitance can be distributed across
LTC3882 devices/pins for improved noise immunity. All
I_{AVG_GND} pins for a PolyPhase rail should be tied together
and connected to a single ground point at or near the
package paddle of the master phase.
Load sharing accuracy is based primarily on the current
sense amplifier offset of each phase (I_{AVG_VOS}) and the
offset of slave current error amplifiers (V_SIOS). These are
given in the Electrical Characteristics (EC) table. Current
sense gain errors between LTC3882 channels will be
negligible. The secondary current sharing loop acts to
average any errors among the phases. Because of this
error averaging and the random nature of these variables,
the EC table limits ensure actual per-phase offset will be
less than or equal to ±300µV for most designs over the
full operating temperature range. This signifies better
than ±2% matching when ∆I_SENSE = 15mV, not including
external factors such as DCR make tolerance.
3882f
54
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