LTC3882_15 Datasheet, PDF (61/104 Pages) Linear Technology – Dual Output PolyPhase Step-Down DC/DC Voltage Mode Controller with Digital Power System Management

LTC3882
APPLICATIONS INFORMATION
associated RUN pin and that GPIO output, with the cathode
of the diode attached to the RUN signal.
All of the above pins have on-chip pull-down transistors
that can sink 3mA at 0.4V. The low-state threshold on
these pins is 1.4V, so ample noise margin exists with 3mA
of current. For 3.3V pins, 3mA of current is produced by
a 1.1k pull-up resistor. Unless there are transient speed
issues associated with the RC time constant of the net, a
10k resistor or larger is generally recommended.
For high speed signals such as SDA, SCL and SYNC, a
lower value resistor may be required. The RC time constant
should be set to 1/3 to 1/5 the required rise time to avoid
timing issues. For a 100pF load and a 400kHz PMBus com-
munication rate, the resistor pull-up on the SDA and SCL
pins with the time constant set to 1/3 the rise time equals
R_PULLUP
=
3
t_RISE
• 100pF
=
1k
The closest 1% resistor value is 1k.
Be careful to minimize parasitic capacitance on the SDA
and SCL lines to avoid communication problems. To
estimate the loading capacitance, monitor the signal in
question and measure how long it takes for the desired
signal to reach approximately 63% of the output value.
This is one time constant.
The SYNC pin has an on-chip pull-down transistor with
the output held low for nominally 250ns when driven by
the LTC3882. If the internal oscillator is set for 500kHz
and the load is 100pF with a 1/3 rise time required, the
resistor calculation is as follows:
R_PULLUP
=
2µs – 250ns
3 •100pF
=
5.83k
The SHARE_CLK output has a nominal period of 10μs
and is pulled low for about 1μs. If the system load on this
shared line is 100pF, the resistor calculation for this line
with a 1/3 rise time is:
R_PULLUP
=
3
9µs
• 100pF
=
30k
The closest 1% resistor is 30.1k.
PMBus Communication and Command Processing
The LTC3882 has a one deep buffer to hold the last data
written for each supported command prior to processing,
as shown in Figure 45. Two distinct parallel sections of
the LTC3882 manage command buffering and command
processing to ensure the last data written to any command
is never lost. When the part receives a new command
from the bus, command data buffering copies the data
into the write command data buffer and indicates to the
internal processor that data for that command should be
handled. The internal processor runs in parallel and per-
forms the sometimes slower task of fetching, converting
(to internal format) and executing commands so marked
for processing.
PMBus
WRITE
CMD
DECODER
DATA
MUX
CALCULATIONS
S
PENDING
R
CMDS
WRITE COMMAND
DATA BUFFER
PAGE
0x00
•••
VOUT_COMMAND 0x21
••
•
MFR_RESET 0xFD
x1
INTERNAL
PROCESSOR
FETCH,
CONVERT
DATA
AND
EXECUTE
3882 F45
Figure 45. Write Command Data Processing
The closest 1% resistor is 5.76k.
If timing errors are occurring or if the SYNC amplitude
is not as large as required, monitor the waveform and
determine if the RC time constant is too long for the
application. If possible reduce the parasitic capacitance.
Otherwise reduce the pull-up resistor sufficiently to assure
proper operation.
Some computationally intensive commands (e.g., timing
parameters, temperatures, voltages and currents) have
internal processor execution times that may be long
relative to PMBus timing. If the part is busy processing
a command, and a new command(s) arrives, execution
may be delayed or processed in a different order than
received. The part indicates when internal calculations are
in process with bit 5 of MFR_COMMON (LTC3882 Calcula-
tions Not Pending). When the internal processor is busy
3882f
For more information www.linear.com/LTC3882
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