LTC3882_15 Datasheet, PDF (44/104 Pages) Linear Technology – Dual Output PolyPhase Step-Down DC/DC Voltage Mode Controller with Digital Power System Management

LTC3882
APPLICATIONS INFORMATION
In addition to PWM bulk input capacitance, a small (0.01μF
to 1μF) bypass capacitor between the chip VINSNS pin and
ground, placed close to the LTC3882, is also suggested. A
small resistor placed between the bulk C_IN and the VINSNS
pin provides further isolation between the two channels.
However, if the time constant of any such R-C network
on the VINSNS pin exceeds 30ns, dynamic line transient
response can be adversely affected.
C_OUT Selection
The selection of C_OUT is primarily determined by the ESR
required to minimize voltage ripple and load step transients.
The output ripple ΔV_OUT is approximately bounded by:
∆V_OUT
≤
∆I_L


ESR +
8
•
f
1
PWM
•
C_OUT


TPD/E/F series, the Kemet T520, T530 and A700 series,
NEC/Tokin NeoCapacitors and Panasonic SP series. Other
suitable capacitor types include Nichicon PL series and
Sprague 595D series. Consult the manufacturer for other
specific recommendations.
Feedback Loop Compensation
The LTC3882 is a voltage mode controller with a second,
dedicated current sharing loop to provide excellent phase-
to-phase current sharing in PolyPhase applications. The
current sharing loop is internally compensated.
While Type 2 compensation for the voltage control loop
may be adequate in some applications (such as with the
use of high ESR bulk capacitors), Type 3 compensation
and ceramic capacitors are recommended for optimum
transient response.
where ΔI_L is the inductor ripple current.
∆I_L
=
L
V_OUT
• f _PWM


1–
V_OUT
V_IN


Since ΔI_L increases with input voltage, the output ripple
voltage is highest at maximum input voltage. Typically
once the ESR requirement is satisfied, the capacitance is
adequate for filtering and has the necessary RMS current
rating.
Manufacturers such as Sanyo, Panasonic and Cornell Du-
bilier should be considered for high performance through-
hole capacitors. The OS-CON semiconductor electrolyte
capacitor available from Sanyo has a good (ESR)(size)
product. An additional ceramic capacitor in parallel with
polarized capacitors is recommended to offset the effect
of lead inductance.
In surface mount applications, multiple capacitors may
have to be paralleled to meet the ESR or transient cur-
rent handling requirements of the application. Aluminum
electrolytic and dry tantalum capacitors are both available
in surface mount configurations. New special polymer
surface mount capacitors offer very low ESR also but
have much lower capacitive density per unit volume. In the
case of tantalum, it is critical that the capacitors are surge
tested for use in switching power supplies. Several excel-
lent output capacitor choices include the Sanyo POSCAP
Figure 22 shows a simplified view of the error amplifier EA
for one LTC3882 channel. The positive input of the error
amplifier is connected to the output of an internal 12-bit
DAC fed by a 1.024V reference, while the negative input is
connected to the FB pin and other internal circuits (not all
shown). R1 is internal to the IC with a value range given
by the R_VSFB parameter in the Electrical Characteristics
table. The output is connected to COMP, from which the
PWM controller derives the required output duty cycle. To
speed up overshoot recovery time, the maximum potential
at the COMP pin is internally clamped.
V_OUT
C2
R1
INTERNAL
C3
R2
R3
–
FB
V_DAC
EA
+
C1
COMP
3882 F22
Figure 22. Type 3 Compensation Circuit
Unlike many regulators that use a transconductance (g_m)
amplifier, the LTC3882 is designed to use an inverting
summing amplifier topology with the FB pin configured
as a virtual ground. This allows feedback gain to be tightly
controlled by external components, which is not possible
with a simple g_m amplifier. The voltage feedback amplifier
3882f
44
For more information www.linear.com/LTC3882