LTC3882_15 Datasheet, PDF (31/104 Pages) Linear Technology – Dual Output PolyPhase Step-Down DC/DC Voltage Mode Controller with Digital Power System Management

LTC3882
OPERATION
Global addressing provides a means for the bus master
to communicate with all LTC3882 devices on the bus
simultaneously. The LTC3882 global addresses of 0x5A
and 0x5B cannot be changed or disabled. Commands sent
to address 0x5A are applied to both channels, as if the
PAGE command were set to 0xFF. Global address 0x5B is
paged, allowing channel-specific control of all LTC3882
devices on the bus. Other LTC device types may respond
at one or both of these global addresses. Reading from
global addresses is strongly discouraged.
Rail addressing provides a means for the bus master to
simultaneously communicate with all channels connected
together to produce a single output voltage (PolyPhase).
While similar to global addressing, the rail address can
be dynamically assigned with the paged MFR_RAIL_AD-
DRESS command, allowing for any logical grouping of
channels that might be required for reliable system control.
Reading from rail addresses is also strongly discouraged.
Device addressing is the most common means used by a
bus master to communicate with an LTC3882. The value
of the device address is set by the combination of ASEL
pin programming and the MFR_ADDRESS command.
Refer to the previous section on Resistor Configuration
Pins for details.
Individual channel addressing allows the bus master
to communicate directly with a specific LTC3882 PWM
channel without first using a PAGE command. Refer to
the PAGE_PLUS commands for additional details.
Use of any of the four types of addressing requires careful
planning to avoid address-related bus conflicts. Commu-
nication to LTC3882 devices at global and rail addresses
should be limited to command write operations.
S START CONDITION
Sr REPEATED START CONDITION
Rd READ (BIT VALUE OF 1)
Wr WRITE (BIT VALUE OF 0)
A ACKNOWLEDGE (BIT SHOULD BE 0), OR
NA NOT ACKNOWLEDGE (BIT SHOULD BE 1)
P STOP CONDITION
PEC PACKET ERROR CODE
MASTER TO SLAVE
SLAVE TO MASTER
... _{CONTINUATION OF PROTOCOL}
3882 F03
Figure 3. PMBus Packet Protocol Diagram Element Key
1
7
1 11
S SLAVE ADDRESS Rd/Wr A P
3882 F04
Figure 4. Quick Command Protocol
1
7
11
8
11
S SLAVE ADDRESS Wr A COMMAND CODE A P
3882 F05
Figure 5. Send Byte Protocol
1
7
11
8
1
8
S SLAVE ADDRESS Wr A COMMAND CODE A
PEC
Figure 6. Send Byte Protocol with PEC
11
AP
3882 F06
For more information www.linear.com/LTC3882
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