LTC3882_15 Datasheet, PDF (62/104 Pages) Linear Technology – Dual Output PolyPhase Step-Down DC/DC Voltage Mode Controller with Digital Power System Management

LTC3882
APPLICATIONS INFORMATION
calculating, bit 5 is cleared. When this bit is set, the part
is ready for another command. An example polling loop
is provided in Figure 46, which ensures that commands
are processed in order while simplifying error handling
routines. MFR_COMMON always returns valid data at
PMBus speeds between 10kHz and 400kHz.
without a NACK, BUSY fault or ALERT notification. The
part can NACK commands for other reasons, however, as
required by the PMBus specification (e.g., an invalid com-
mand or data). An example of a robust command write
algorithm for the VOUT_COMMAND register is provided
in Figure 46.
// wait until bits 6, 5, and 4 of MFR_COMMON are all set
do
{
mfrCommonValue = PMBUS_READ_BYTE(0xEF);
partReady = (mfrCommonValue & 0x68) == 0x68;
}while(!partReady)
// now the part is ready to receive the next command
PMBUS_WRITE_WORD(0x21, 0x2000); //write VOUT_COMMAND to 2V
Figure 46. Example of a Polling Loop to Write VOUT_COMMAND
When the part receives a new command while it is busy,
it will communicate this condition using standard PMBus
protocol. Depending on part configuration it may either
NACK the command or return all ones (0xFF) for reads. It
may also generate a BUSY fault and ALERT notification,
or stretch the SCL clock low. For more information refer
to PMBus Specification V1.2, Part II, Section 10.8.7 and
SMBus V2.0 section 4.3.3. Clock stretching can be enabled
by asserting bit 1 of MFR_CONFIG_ALL_LTC3882. Clock
stretching will only occur if enabled and the bus com-
munication speed exceeds 100kHz.
PMBus protocols for busy devices are well accepted
standards but can make writing system level software
somewhat complex. The part provides three handshaking
status bits which reduce this complexity while enabling
robust system level communication. The three hand shak-
ing status bits are in the MFR_COMMON register. When
the part is busy executing an internal operation, it will
clear bit 6 of MFR_COMMON (LTC3882 Not BUSY). When
internal calculations are in process, the part will clear bit
5 of MFR_COMMON (LTC3882 Calculations Not Pending).
When the part is busy specifically because it is transitioning
V_OUT (margining, off/on, moving to a new VOUT_COM-
MAND, etc.) it will clear bit 4 of MFR_COMMON (LTC3882
Output Not In Transition). These three status bits can be
polled with a PMBus read byte of the MFR_COMMON
register until all three bits are set. A command immediately
following all these status bits being set will be accepted
It is recommended that all command writes be preceded
with such a polling loop to avoid the extra complexity of
dealing with busy behavior or unwanted ALERT notifica-
tions. A simple way to achieve this is to embed the polling
in subroutines to write command bytes and words. This
polling mechanism will allow system software to remain
clean and simple while robustly communicating with the
part. For a detailed discussion of these topics and other
special cases please refer to the application note section
located at www.linear.com/designtools/app_notes.
When communicating using bus speeds at or below
100kHz, the polling mechanism previously shown provides
a simple solution that ensures robust communication with-
out clock stretching. At bus speeds in excess of 100kHz,
it is strongly recommended that the part be enabled to
use clock stretching, requiring a PMBus master that sup-
ports that function. Clock stretching does not allow the
LTC3882 to communicate reliably on busses operating
above 400kHz. Operating the LTC3882 with PMBus SCL
rates above 400kHz is not recommended. System software
that detects and properly recovers from the standard PM-
Bus NACK responses or BUSY faults described in PMBus
Specification V1.2, Part II, Section 10.8.7 is required to
communicate above 100kHz without clock stretching.
Refer to Application Note 135 for techniques that may also
apply to implement a robust PMBus interface to the LTC3882.
Status and Fault Log Management
Due to internal operation, very infrequently the LS byte of
STATUS_WORD may be inconsistent with the state of bits
in the MS byte. This condition is quite transient and can
normally be resolved by simply re-reading STATUS_WORD.
If power is lost during an internal store of a fault log
to EEPROM, a partial write of the log can result. In this
situation, the LTC3882 will not indicate that a fault log is
present the next time adequate supply voltage is applied
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For more information www.linear.com/LTC3882