LTC3882_15 Datasheet, PDF (58/104 Pages) Linear Technology – Dual Output PolyPhase Step-Down DC/DC Voltage Mode Controller with Digital Power System Management

LTC3882
APPLICATIONS INFORMATION
in the later section covering PMBus command details, as
well as Application Note 137.
Resistor Configuration Pins
As a factory default, the LTC3882 is programmed to use
external resistor configuration, allowing output voltage,
PWM frequency and phasing, and the PMBus address to
be set without programming the part through its serial
interface or purchasing devices with custom EEPROM
contents. The RCONFIG pins all require a resistor divider
between V_DD25 and GND. The RCONFIG pins are only
interrogated at initial power up and during a reset, so
modifying their values on the fly is not recommended.
RCONFIG pins on the same IC can be shared with a single
resistor divider if they require identical programming.
Resistors with a tolerance of 1% or better must be used
to assure proper operation. In the following tables, R_TOP
is connected between V_DD25 and the RCONFIG pin, while
R_BOT is connected between the pin and GND. Noisy clock
signals should not be routed near these pins.
Table 8. V_{OUTn_CFG} Resistor Programming
R_TOP (kΩ)
R_BOT (kΩ)
0 or Open
Open
10
23.2
10
15.8
16.2
20.5
16.2
17.4
20
17.8
20
15
20
12.7
20
11
24.9
11.3
24.9
9.09
24.9
7.32
24.9
5.76
24.9
4.32
V_OUT (V)
From EEPROM
5.0
3.3
2.5
1.8
1.5
1.35
1.25
1.2
1.15
1.1
1.05
0.9
0.75
to programming a VOUT_COMMAND value of 1.8V. Refer
to the Operations section for related parameters that are
also automatically set as a percentage of the programmed
V_OUT if resistor configuration pins are used to determined
output voltage.
Table 9. FREQ_CFG Resistor Programming
R_TOP (kΩ)
0 or Open
20
20
20
20
24.9
24.9
24.9
24.9
24.9
30.1
30.1
Open
R_BOT (kΩ)
Open
17.8
15
12.7
11
11.3
9.09
7.32
5.76
4.32
3.57
1.96
0
SWITCHING
FREQUENCY (kHz)
from EEPROM
1250
1000
900
750
600
500
450
400
350
300
250
External SYNC Only
Note that if SYNC pins are shared between LTC3882s,
only one SYNC output should be enabled. All other SYNC
outputs should be disabled. For example, if configuring
two LTC3882s as a 4-phase rail operating at a frequency
of 600kHz, both devices should have R_TOP of 24.9kΩ and
R_BOT of 11.3kΩ on the FREQ_CFG pin. In this case, select-
ing R_TOP of 24.9kΩ and R_BOT of 9.09kΩ for PHAS_CFG on
the first IC (clock master) affords 180° of phase separation
and enables the SYNC output. The second device should
have R_TOP of 20kΩ and R_BOT of 12.7kΩ on PHAS_CFG,
to )disable its SYNC output and run its phases with 180°
of separation in quadrature with the first IC. Only mix
phase selections that have the same maximum duty cycle
specified. Refer to Tables 9 and 10.
30.1
3.57
0.65
30.1
1.96
0.6
Open
0
Output OFF*
(V_OUT from EEPROM)
*OPERATION value and RUNn pin must both command the channel to
start from this configuration.
Output voltage can be set as shown in Table 8. For example,
setting R_TOP to 16.2kΩ and R_BOT to 17.4kΩ is equivalent
The LTC3882 address is selected based on the program-
ming of the two configuration pins ASEL0 and ASEL1
according to Table 11. ASEL0 programs the bottom four
bits of the device address for the LTC3882, and ASEL1
programs the three most-significant bits. Either portion
of the address can also be retrieved from the MFR_AD-
DRESS value in EEPROM. If both pins are left open, the
full 7-bit MFR_ADDRESS value stored in EEPROM is used
3882f
58
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