LTC3882_15 Datasheet, PDF (11/104 Pages) Linear Technology – Dual Output PolyPhase Step-Down DC/DC Voltage Mode Controller with Digital Power System Management

TYPICAL PERFORMANCE CHARACTERISTICS
LTC3882
Temperature ADC TUE
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–45 –25 –5 15 35 55 75 95 115
ACTUAL TEMPERATURE (°C)
3882 G22
SHARE_CLK Frequency vs
Temperature
110
105
100
95
90
–50 –30 –10 10 30 50 70
TEMPERATURE (°C)
90 110
3882 G23
IC Operating Current vs
Temperature
31.0
V_CC = 14V
30.8
30.6
30.4
30.2
30.0
29.8
29.6
29.4
–40 –20
0 20 40 60 80 100 120
TEMPERATURE (°C)
3882 G24
PIN FUNCTIONS
COMP0/COMP1 (Pin 1/Pin 29): Error Amplifier Outputs.
PWM duty cycle increases with this control voltage. These
are true low impedance outputs and cannot be directly
connected together when active. For PolyPhase operation,
wiring FB to V_DD33 will three-state the error amplifier output
of that channel, making it a slave. PolyPhase control is
then implemented in part by connecting all slave COMP
pins together to one master error amplifier output.
TSNS0/TSNS1 (Pin 2/Pin 3): External Temperature Sense
Inputs. The LTC3882 supports two methods of calcula-
tion of external temperature based on forward-biased P/N
junctions between these pins and GND.
BG0(EN0)/BG1(EN1) (Pin 6/Pin 28): PWM Multi-Function
Control Pins. These pins can be digitally programmed to
provide direct bottom FET control (BGn function) or PWM
enable control (ENn function), depending on external gate
driver requirements. These pins can also function as inputs
for three-state PWM protocol selection and should be left
open if not used.
TG0(PWM0)/TG1(PWM1) (Pin 7/Pin 27): PWM Multi-
Function Control Outputs. These pins can be digitally pro-
grammed to provide direct top FET control (TGn function)
or single-wire PWM switching control (PWMn function),
depending on external gate driver requirements.
VINSNS (Pin 4): V_IN Supply Sense. Connect to the V_IN
power supply to provide line feedforward compensation.
A change in V_IN immediately modulates the input to the
PWM comparator and inversely changes the pulse width
to provide excellent transient line regulation and fixed
modulator voltage gain. An external lowpass filter can be
added to this pin to prevent noisy signals from affecting
the loop gain.
I_{AVG_GND} (Pin 5): I_AVG Ground Reference. The same
I_{AVG_GND} should be shared between all channels of a
PolyPhase rail and connected to system ground at a single
point. I_{AVG_GND} may be wired directly to GND on ICs that
do not share phases with other chips.
SYNC (Pin 8): External Clock Synchronization Input and
Open-Drain Output. If desired, an external clock can be
applied to this pin to synchronize the internal PWM chan-
nels. If the LTC3882 is configured as a clock master, this
pin will also pull to ground at the selected PWM switching
frequency with a 125ns pulse width. A pull-up resistor to
3.3V is required in the application if SYNC is driven by any
LTC3882. Minimize the capacitance on this line to ensure
its time constant is fast enough for the application.
SCL (Pin 9): Serial Bus Clock Input. A pull-up resistor to
3.3V is required in the application.
SDA (Pin 10): Serial Bus Data Input and Output. A pull-up
resistor to 3.3V is required in the application.
3882f
For more information www.linear.com/LTC3882
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