LTC3882_15 Datasheet, PDF (43/104 Pages) Linear Technology – Dual Output PolyPhase Step-Down DC/DC Voltage Mode Controller with Digital Power System Management

LTC3882
APPLICATIONS INFORMATION
The LTC3882 may require as much as 70ms from the be-
ginning of initialization to retrieve and set the programmed
protocol from EEPROM. This protocol is always applied
before any PWM operation begins. However, if the initial-
ization is due to a rapidly applied V_IN system supply, the
LTC3882 PWM outputs may not be in the best state to
maintain the desired level of power FET control during this
period. This is especially true if V_CC powers the controller
and also has ramp-up delay after V_IN is applied.
In the case of rapidly applied V_IN, the system supply will
immediately be available to provide power to the top FET,
and the high impedance PWM output(s) can easily be
moved with dV/dt current through parasitic capacitances.
This situation could result in damage to the power stage or
loss of V_OUT control, depending on the power state design.
It is highly recommended that a resistor no larger than
10k be considered to help maintain power stage control
during initialization in the following cases. For protocol
0x1, this resistor should be placed between EN and ground.
For protocol 0x3, this resistor should be placed between
TG and ground. For protocol 0x2, it may be necessary to
actively pull EN low with an external signal FET controlled
by a separate POR circuit. Careful evaluation of the actual
power stage during power-up is recommended to determine
if these additional safety measures are needed.
C_IN Selection
The input bypass capacitance for an LTC3882 circuit needs
to have ESR low enough to keep the supply drop low as the
top MOSFETs turn on, RMS current capability adequate to
withstand the ripple current at the input, and a capacitance
value large enough to maintain the input voltage until the
input supply can make up the difference. Generally, a ca-
pacitor that meets the first two requirements (particularly
a non-ceramic type) will have far more capacitance than is
required to keep capacitance-based droop under control.
The input capacitance voltage rating should be at least 1.4
times the maximum input voltage. Power loss due to ESR
occurs as I²R dissipation in the capacitor itself. The input
capacitor RMS current and its impact on any preceding
input network is reduced by PolyPhase architecture. It can
be shown that the worst case RMS current occurs when
only one controller is operating. The controller with the
highest (V_OUT)(I_OUT) product should be used to determine
the maximum RMS current requirement. Increasing the
output current drawn from the other out-of-phase control-
ler will decrease the input RMS ripple current from this
maximum value. Two channel out-of-phase operation
typically reduces the input capacitor RMS ripple current
by a factor of 30% to 70%.
In continuous inductor conduction mode, the source cur-
rent of the top power MOSFET is approximately a square
wave of duty cycle V_OUT/V_IN. The maximum RMS capacitor
current in this case is given by:
( ) _{IRMS ≈IOUT(MAX)}
V_OUT V_IN – V_OUT
V_IN
This formula has a maximum at V_IN = 2V_OUT, where
I_RMS = I_OUT/2
This simple worst-case condition is commonly used for
design because even significant deviations do not offer
much relief.
Note that manufacturer ripple current ratings for capacitors
are often based on only 2000 hours of life. This makes
it advisable to further derate the capacitor or to choose
a capacitor rated at a higher temperature than required.
Several capacitors may also be paralleled to meet size or
height requirements in the design. Always consult the
manufacturer if there is any question.
Ceramic, tantalum, semiconductor electrolyte (OS-CON),
hybrid conductive polymer (SUNCON) and switcher-rated
electrolytic capacitors can be used as input capacitors, but
each has drawbacks. Ceramics have high voltage coeffi-
cients of capacitance and may have audible piezoelectric
effects; tantalums need to be surge-rated; OS-CONs suffer
from higher inductance, larger case size and limited surface
mount applicability; and electrolytic capacitors have higher
ESR and can dry out. Sanyo OS-CON SVP(D) series, Sanyo
POSCAP TQC series, or Panasonic EE-FT series aluminum
electrolytic capacitors can be used in parallel with a couple
of high performance ceramic capacitors as an effective
means of achieving low ESR and high bulk capacitance.
For more information www.linear.com/LTC3882
3882f
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