LTC3882_15 Datasheet, PDF (59/104 Pages) Linear Technology – Dual Output PolyPhase Step-Down DC/DC Voltage Mode Controller with Digital Power System Management

LTC3882
APPLICATIONS INFORMATION
Table 10. PHAS_CFG Resistor Programming
R_TOP (kΩ)
0 or Open
R_BOT (kΩ)
Open
θ_SYNC TO θ₀
From EEPROM
20
15
135°
20
12.7
90°
20
11
45°
24.9
11.3
0°
24.9
9.09
0°
24.9
7.32
120°
24.9
5.76
60°
24.9
4.32
0°
30.1
3.57
0°
30.1
1.96
0°
Open
0
0°
θ_SYNC TO θ₁
From EEPROM
315°
270°
225°
180°
180°
300°
240°
180°
120°
180°
120°
MAXIMUM DUTY CYCLE
See MFR_PWM_CONFIG
87.5%
SYNC OUTPUT DISABLED
From EEPROM
Yes
No
83.3%
Yes
No
to determine the device address. In the 4-phase example
above, it is recommended that one or both ASELn pins on
both parts be programmed to create two unique addresses.
The LTC3882 also responds to 7-bit global addresses 0x5A
and 0x5B. MFR_ADDRESS and MFR_RAIL_ADDRESS
should not be set to either of these values.
Table 11. ASELn Resistor Programming
ASEL1
R_TOP (kΩ) R_BOT (kΩ)
LTC3882 DEVICE
ADDRESS BITS[6:4]
BINARY HEX
0 or Open Open
from EEPROM
10
23.2
10
15.8
16.2
20.5
16.2
17.4
20
17.8
20
15
20
12.7
20
11
24.9
11.3
111
7
24.9
9.09
110
6
24.9
7.32
101
5
24.9
5.76
100
4
24.9
4.32
011
3
30.1
3.57
010
2
30.1
1.96
001
1
Open
0
000
0
ASEL0
LTC3882 DEVICE
ADDRESS BITS[3:0]
BINARY HEX
from EEPROM
1111
F
1110
E
1101
D
1100
C
1011
B
1010
A
1001
9
1000
8
0111
7
0110
6
0101
5
0100
4
0011
3
0010
2
0001
1
0000
0
Internal Regulator Outputs
The V_DD33 pin provides supply current for much of the
internal LTC3882 analog circuitry at a nominal value of
3.3V. The LTC3882 features an internal linear regulator
that can be used to supply 3.3V to V_DD33 from a higher
voltage V_CC supply (up to 12V nominal). Use of this LDO
is optional. The LTC3882 will also accept an external 3.3V
supply attached to this pin if V_CC and V_DD33 are shorted. If
the internal 3.3V LDO is used, it can supply a peak current
of 85mA (including internal consumption), and the V_DD33
regulator output must be bypassed to GND with a low ESR
X5R or X7R ceramic capacitor with a value of 2.2μF. If an
external source supplies V_DD33, a local low ESR bypass
capacitor with a value between 0.01μF and 0.1μF should
be placed directly between the V_DD33 and GND pins.
Do not draw more than 20mA from the internal 3.3V regula-
tor for the host system, governed by IC power dissipation
as discussed in the next section. This limit includes current
required for external pull up resistors for the LTC3882 that
are terminated to V_DD33.
V_DD33 powers a second internal 2.5V LDO whose output
is present on V_DD25. This 2.5V supply provides power for
much of the internal processor logic on the LTC3882. The
V_DD25 output should be bypassed directly to GND with a
low ESR X5R or X7R ceramic capacitor with a value of
1μF or greater. Do not draw any external system current
from this supply beyond that required for LTC3882 specific
configuration resistor dividers.
3882f
For more information www.linear.com/LTC3882
59