LTC3882_15 Datasheet, PDF (52/104 Pages) Linear Technology – Dual Output PolyPhase Step-Down DC/DC Voltage Mode Controller with Digital Power System Management

LTC3882
APPLICATIONS INFORMATION
When the system is turned off, rails will shut down in the
same order as they turn on, as shown in Figure 36. If a
different sequence is required, the circuit must be rewired
or delays must be added by programming TON_DELAY or
TOFF_DELAY. A fundamental limitation of this application is
the inability of upstream rails to detect a start-up failure of
downstream rails. Due to this, cascade sequencing should
not be implemented without an external fast supervisor
to monitor downstream rails and assert a system fault if
problems occur.
1V/DIV
VOUT4
VOUT3
VOUT2
VOUT1
100ms/DIV
3882 F36
Figure 36. Cascade Sequencing Waveforms
that limit is set to 0s (infinite). In that case, the mode is
engaged as soon as the above conditions are satisfied.
Using AVP
The LTC3882 features digitally programmable active volt-
age positioning (AVP), where output voltage set point is
automatically adjusted as a function of output current at
the full bandwidth of the converter. AVP normally entails
specifying an output load line for a voltage mode switcher
to allow current sharing between master phases connected
in parallel. While AVP can be used to this effect in LTC3882
applications, use of the LTC3882 I_AVG current sharing
control loop is recommended instead. This will produce
more accurate sharing across a wider number of phases
without degrading supply output impedance.
However, AVP can still be used to great benefit in LTC3882
applications. AVP can be applied to minimize the size of
output filter capacitance for some allowed output voltage
variation over the anticipated load range. An example of
AVP is shown in Figure 37.
Using Output Voltage Servo
For best output voltage accuracy, enable digital
servo mode on the master phase by setting bit 6 of
MFR_PWM_MODE_LTC3882. In digital servo mode, the
LTC3882 will adjust the regulated output voltage based on
its related ADC voltage reading. Every 100ms the digital
servo loop will step the LSB of the DAC (nominally 1.375mV
or 0.6875mV depending on the voltage range bit) until the
output is at the correct ADC reading.
When the master channel is turned on, digital servo is
enabled after all of the following conditions are satisfied.
• MFR_PWM_MODE_LTC3882 Bit 6 Is Set
• The TON_RISE Sequence Is Complete
• A VOUT_UV_FAULT Is Not Present
• An IOUT_OC_FAULT Is Not Present
• MFR_AVP = 0%
Digital servo mode then engages after TON_MAX_
FAULT_LIMIT has expired as shown in Figure 29, unless
I_O
(10A/DIV)
AVP DISABLED
V_OUT
(50mV/DIV)
I_O
(10A/DIV)
WITH AVP
173mV
V_OUT
(50mV/DIV)
108mV
LOOP: BW = 118kHz, PM = 58°, GM = 7dB
3882 F37
Figure 37. Active Voltage Positioning
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For more information www.linear.com/LTC3882