LTC3882_15 Datasheet, PDF (13/104 Pages) Linear Technology – Dual Output PolyPhase Step-Down DC/DC Voltage Mode Controller with Digital Power System Management

LTC3882
mented in part by connecting all slave I_AVG pins together
to the master I_AVG output. This pin should be left open on
channels that control single-phase outputs.
FB0/FB1 (Pin 40/Pin 30): Error Amplifier Inverting Inputs.
These pins provide an internally scaled version of the
output voltage for use in loop compensation. Refer to the
Applications Information section for additional details on
compensating the output voltage control loop with external
components.
GND (Exposed Pad Pin 41): Ground and V_SENSE1–. All
small-signal and compensation components should
connect to this pad, which also serves as the negative
voltage sense input for channel 1. The exposed pad must
be soldered to a suitable PCB copper ground plane for
proper electrical operation and to obtain the specified
package thermal resistance.
BLOCK DIAGRAM
SHARE_CLK
WP
RAM
R_CONFIG
PMBus
ROM
EEPROM
MCU AND
CUSTOM
LOGIC
2.5V
REGULATOR
SYNC
V_CC
V_DD33
VINSNS
PWM0
V_SENSE0±
I_SENSE0±
TSNS0
PWM1
V_SENSE1±
I_SENSE1±
TSNS1
VOLTAGE
REFERENCE
PLL
V_REF
3.3V
REGULATOR
BIAS AND
HOUSEKEEPING
ANALOG
MUX
16-BIT
ADC
INTERNAL
TEMPERATURE
12-BIT
DAC
VINSNS
PWM0
I_SENSE0±
I_AVG0
V_SENSE0±
PWM0/EN0
I_{AVG_GND}
PWM1/EN1
12-BIT
DAC
PWM1
INTERNAL DATA BUS
V_SENSE1±
I_SENSE1±
I_AVG1
VINSNS
3882 BD
For more information www.linear.com/LTC3882
3882f
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