LTC3882_15 Datasheet, PDF(34/104 Page) Linear Technology – Dual Output PolyPhase Step-Down DC/DC Voltage Mode Controller with Digital Power System Management

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LTC3882_15 Datasheet, PDF (34/104 Pages) Linear Technology – Dual Output PolyPhase Step-Down DC/DC Voltage Mode Controller with Digital Power System Management

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LTC3882

OPERATION

Serial Bus Timeout

The LTC3882 implements a timeout feature to avoid hanging

the serial interface. The data packet timer begins running

at the first START event before the SLAVE ADDRESS write

byte and ends with the STOP bit. Packet transmission must

be completed before the timer expires, or the LTC3882 will

tri-state the bus and ignore all message data. The data

packet includes the SLAVE ADDRESS byte, COMMAND

CODE byte, repeated START and SLAVE ADDRESS byte

(if a read operation), all ACKNOWLEDGE and flow control

bits (R/W) and all data bytes.

The packet timer is typically set to 30ms. If bit 3 of

MFR_CONFIG_ALL_LTC3882 is set, this period is extended

to 255ms. The LTC3882 automatically allows a packet

transmission time of 255ms for MFR_FAULT_LOG block

reads regardless of the setting of this bit. In no circum-

stances will the timeout period be less than the tTIMEOUT

specification (25ms minimum).

The LTC3882 supports the full PMBus frequency range

of 10kHz to 400kHz.

Serial Communication Errors

The LTC3882 supports the optional PMBus packet error

checking protocol. This protocol appends a packet error

code (PEC) to the end of applicable message transfers to

improve communication reliability. The PEC is a CRC-8

error-checking byte calculated by the bus device sending

the last data byte. Refer to SMBus specification 1.2 or

higher for additional implementation details. All LTC3882

read operations will return a valid PEC if the bus master

requests it. If bit 2 in the MFR_CONFIG_ALL_LTC3882

command is set, the IC will not act in response to a bus

write operation unless a valid PEC is also received from

the host.

PEC errors on command writes, attempts to access

unsupported commands, or writing invalid data to sup-

ported commands all cause the LTC3882 to generate a

CML fault. The CML bit is then set in the STATUS_BYTE

and STATUS_WORD commands, and the appropriate bit

is set in the STATUS_CML command.

3882f

For more information www.linear.com/LTC3882

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