LTC3882_15 Datasheet, PDF (53/104 Pages) Linear Technology – Dual Output PolyPhase Step-Down DC/DC Voltage Mode Controller with Digital Power System Management

LTC3882
APPLICATIONS INFORMATION
MFR_VOUT_AVP specifies the percent reduction in pro-
grammed V_OUT from no load at an output current value
equal to IOUT_WARN_LIMIT. LTC3882 AVP supports a
maximum reduction in V_OUT of 15%, corresponding to
a ±7.5% tolerance about a nominal output voltage at
roughly 50% load. In order to effectively use AVP, apply
the following steps.
1. Set IOUT_OC_WARN_LIMIT. This specifies the master
phase output current at which the programmed AVP
level will apply. Generally this is above the 100% load
point to avoid spurious warnings at full load.
2. VOUT_COMMAND should be set to the value of V_OUT de-
sired with no load on the output. VOUT_MARGIN_HIGH/
LOW also specify no-load values when AVP is enabled.
AVP on the LTC3882 can only reduce the output from
these levels.
3. Set MFR_VOUT_AVP to a percentage that produces the
desired output excursion as a function of current.
For example, if the goal is to allow a 2.5% output change
on a 3.3V 6-phase supply rated at 120A during an output
load step from 20% to 80%, the following parameters
should be programmed.
First set an output current warning level for the master (one
of six phases) just slightly higher than the rated full load
to avoid spurious warnings. Typically this same setting
would also be applied to the five slave phases.
IOUT_OC_WARN_LIMIT = 1.1 • 120A/6 = 22A
The open circuit output voltage calculation for the master
phase must reflect that the AVP specification in this case
only covers an output load swing of 60%.
VOUT_COMMAND = 3.3V(1 + 0.5 • 0.025/0.6)

= 3.3687V
The AVP calculation must then account for the fact that
IOUT_OC_WARN_LEVEL is set higher than the 100%
load point.
MFR_VOUT_AVP
=
100%
•
1.1• 2 •(3.3687
3.3687
–
3.3)
= 4.487%
With the output voltage at 3.3V at 50% load these set-
tings will move V_OUT from approximately 3.34V to about
3.26V when the output load of the rail moves from 24A
to 96A. Note that V_OUT will drop to 3.23V at full load in
this design example.
Digital output servo mode is automatically disabled if
AVP is enabled on a master phase. AVP is active during
all output ramping when enabled (e.g., a TON_RISE se-
quence). AVP is disabled on master phases by program-
ming MFR_VOUT_AVP to 0.0% (factory default). AVP is
automatically disabled on phases configured as slaves
(FB tied to V_DD33).
Because of related ISENSE input offsets, increased output
voltage error can occur at all operating currents when AVP
is engaged. To minimize this error a calibration offset can
be added to the master phase VOUT_COMMAND value
based on the READ_VOUT value obtained when operat-
ing at a known output current of at least 20% of full load
(READ_IOUT). The necessary correction, which will typi-
cally be less than several percent of the no load output
voltage, is calculated as:
VOS = VOUT_COMMAND
•


1–
MFR_VOUT_AVP •READ_IOUT
100 •IOUT_OC_WARN_LIMIT


– READ_VOUT
PWM Frequency Synchronization
The LTC3882 incorporates an internal phase-locked loop
(PLL) which enables synchronization of both PWM chan-
nels (falling edge of TG) to an external CMOS clock from
250kHz to 1.25MHz. The PLL is locked to the falling edge
of the SYNC pin clock signal. This PLL also generates
very accurate channel phase relationships which can be
selected with the MFR_PWM_CONFIG_LTC3882 com-
mand. For PolyPhase applications, all phases should be
spaced evenly in the phase diagram for best results. For
instance, a 4-phase system should use a separation of
90° between channels.
The PLL has a lock detection circuit. If the PLL should lose
lock during operation, bit 4 of the STATUS_MFR_SPECIFIC
command is asserted and the ALERT pin is pulled low,
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