XP2 Datasheet, PDF (90/92 Pages) Lattice Semiconductor – LatticeXP2 Family Data Sheet

LatticeXP2 Family Data Sheet
Supplemental Information
May 2007
Data Sheet DS1009
For Further Information
A variety of technical notes for the LatticeXP2 FPGA family are available on the Lattice Semiconductor web site at
www.latticesemi.com/products/fpga/xp2.
• LatticeXP2 sysIO Usage Guide (TN1136)
• LatticeXP2 Memory Usage Guide (TN1137)
• LatticeXP2 High Speed I/O Interface (TN1138)
• LatticeXP2 sysCLOCK PLL Design and Usage Guide (TN1126)
• Power Estimation and Management for LatticeXP2 Devices (TN1139)
• LatticeXP2 sysDSP Usage Guide (TN1140)
• LatticeXP2 sysCONFIG Usage Guide (TN1141)
• LatticeXP2 Configuration Encryption and Security Usage Guide (TN1142)
• Minimizing System Interruption During Configuration Using TransFR Technology (TN1087)
• LatticeXP2 Dual Boot Usage Guide (TN1144)
• LatticeXP2 Soft Error Detection (SED) Usage Guide (TN1130)
For further information on interface standards refer to the following web sites:
• JEDEC Standards (LVTTL, LVCMOS, SSTL, HSTL): www.jedec.org
• PCI: www.pcisig.com
© 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
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