XP2 Datasheet, PDF (70/92 Pages) Lattice Semiconductor – LatticeXP2 Family Data Sheet

Lattice Semiconductor
DC and Switching Characteristics
LatticeXP2 Family Data Sheet
LatticeXP2 Family Timing Adders^{1, 2, 3} (Continued)
Over Recommended Operating Conditions
Buffer Type
Description
-7
LVCMOS25_4mA
LVCMOS 2.5 4mA drive, slow slew rate
1.05
LVCMOS25_8mA
LVCMOS 2.5 8mA drive, slow slew rate
0.78
LVCMOS25_12mA LVCMOS 2.5 12mA drive, slow slew rate
0.59
LVCMOS25_16mA LVCMOS 2.5 16mA drive, slow slew rate
0.81
LVCMOS25_20mA LVCMOS 2.5 20mA drive, slow slew rate
0.61
LVCMOS18_4mA
LVCMOS 1.8 4mA drive, slow slew rate
1.01
LVCMOS18_8mA
LVCMOS 1.8 8mA drive, slow slew rate
0.72
LVCMOS18_12mA LVCMOS 1.8 12mA drive, slow slew rate
0.53
LVCMOS18_16mA LVCMOS 1.8 16mA drive, slow slew rate
0.74
LVCMOS15_4mA
LVCMOS 1.5 4mA drive, slow slew rate
0.96
LVCMOS15_8mA
LVCMOS 1.5 8mA drive, slow slew rate
-0.53
LVCMOS12_2mA
LVCMOS 1.2 2mA drive, slow slew rate
0.90
LVCMOS12_6mA
LVCMOS 1.2 6mA drive, slow slew rate
-0.55
PCI33
3.3V PCI
-0.29
1. Timing Adders are characterized but not tested on every device.
2. LVCMOS timing measured with the load specified in Switching Test Condition table.
3. All other standards tested according to the appropriate specifications.
4. These timing adders are measured with the recommended resistor values.
Timing v. A 0.12
-6
1.43
1.15
0.96
1.18
0.98
1.38
1.08
0.90
1.11
1.33
-0.26
1.27
-0.29
-0.01
-5
1.81
1.52
1.33
1.55
1.35
1.75
1.45
1.26
1.48
1.71
0.00
1.65
-0.02
0.26
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3-26