XP2 Datasheet, PDF (71/92 Pages) Lattice Semiconductor – LatticeXP2 Family Data Sheet

Lattice Semiconductor
DC and Switching Characteristics
LatticeXP2 Family Data Sheet
sysCLOCK PLL Timing
Over Recommended Operating Conditions
Parameter
Description
Conditions
f_IN
f_OUT
Input Clock Frequency (CLKI, CLKFB)
Output Clock Frequency (CLKOP,
CLKOS)
f_OUT2
K-Divider Output Frequency
CLKOK
CLKOK2
f_VCO
PLL VCO Frequency
f_PFD
Phase Detector Input Frequency
AC Characteristics
t_DT
t_CPA
t_PH⁴
t_OPJIT¹
t_SK
t_OPW
t_LOCK²
Output Clock Duty Cycle
Coarse Phase Adjust
Output Phase Accuracy
Output Clock Period Jitter
Input Clock to Output Clock Skew
Output Clock Pulse Width
PLL Lock-in Time
Default duty cycle selected ³
f_OUT > 400 MHz
100 MHz < f_OUT < 400 MHz
f_OUT < 100 MHz
N/M = integer
At 90% or 10%
25 to 435MHz
10 to 25MHz
t_IPJIT
Input Clock Period Jitter
t_FBKDLY
External Feedback Delay
t_HI
Input Clock High Time
90% to 90%
t_LO
Input Clock Low Time
10% to 10%
T_R / t_F
Input Clock Rise/Fall Time
10% to 90%
t_RSTKW
Reset Signal Pulse Width (RSTK)
t_RSTW
Reset Signal Pulse Width (RST)
1. Jitter sample is taken over 10,000 samples of the primary PLL output with clean reference clock.
2. Output clock is valid after t_LOCK for PLL reset and dynamic delay adjustment.
3. Using LVDS output buffers.
4. Relative to CLKOP.
Timing v. A 0.12
Min.
10
10
0.078
3.3
435
10
45
-5
-5
—
—
—
—
1
—
—
—
—
0.5
0.5
—
10
500
Typ.
—
—
—
—
—
—
50
0
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max. Units
435 MHz
435 MHz
217.5
145
870
435
MHz
MHz
MHz
MHz
55
5
5
±50
±125
0.025
±240
—
50
100
±200
10
—
—
1
—
—
%
%
%
ps
ps
UIPP
ps
ns
µs
µs
ps
ns
ns
ns
ns
ns
ns
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