XP2 Datasheet, PDF (72/92 Pages) Lattice Semiconductor – LatticeXP2 Family Data Sheet

Lattice Semiconductor
DC and Switching Characteristics
LatticeXP2 Family Data Sheet
LatticeXP2 sysCONFIG Port Timing Specifications
Over Recommended Operating Conditions
Parameter
Description
sysCONFIG POR, Initialization and Wake Up
t_ICFG
Minimum Vcc to INITN High
t_VMC
Time from tICFG to valid Master CCLK
t_PRGMRJ
PROGRAMN Pin Pulse Rejection
t_PRGM
PROGRAMN Low Time to Start Configuration
t_DINIT
PROGRAMN High to INITN High Delay
t_DPPINIT
Delay Time from PROGRAMN Low to INITN Low
t_DPPDONE
Delay Time from PROGRAMN Low to DONE Low
t_IODISS
User I/O Disable from PROGRAMN Low
t_IOENSS
User I/O Enabled Time from CCLK Edge During Wake-up Sequence
t_MWC
Additional Wake Master Clock Signals after DONE Pin High
sysCONFIG SPI Port (Master)
t_CFGX
INITN High to CCLK Low
t_CSSPI
INITN High to CSSPIN Low
t_CSCCLK
CCLK Low before CSSPIN Low
t_SOCDO
CCLK Low to Output Valid
t_CSPID
CSSPIN[0:1] Low to First CCLK Edge Setup Time
f_MAXSPI
Max CCLK Frequency
t_SUSPI
SOSPI Data Setup Time Before CCLK
t_HSPI
SOSPI Data Hold Time After CCLK
sysCONFIG SPI Port (Slave)
f_MAXSPIS
t_RF
t_STCO
t_STOZ
t_STSU
t_STH
t_STCKH
t_STCKL
t_STVO
t_SCS
t_SCSS
t_SCSH
Slave CCLK Frequency
Rise and Fall Time
Falling Edge of CCLK to SOSPI Active
Falling Edge of CCLK to SOSPI Disable
Data Setup Time (SISPI)
Data Hold Time (SISPI)
CCLK Clock Pulse Width, High
CCLK Clock Pulse Width, Low
Falling Edge of CCLK to Valid SOSPI Output
CSSPISN High Time
CSSPISN Setup Time
CSSPISN Hold Time
Min
—
—
—
50
—
—
—
—
—
0
—
—
0
—
2cyc
—
7
10
—
50
—
—
8
10
0.02
0.02
—
25
25
25
Max
Units
50
ms
2
µs
12
ns
—
ns
1
ms
50
ns
50
ns
35
ns
25
ns
—
cycles
1
2
—
15
600+6cyc
20
—
—
µs
µs
ns
ns
ns
MHz
ns
ns
25
MHz
—
mV/ns
20
ns
20
ns
—
ns
—
ns
200
µs
200
µs
20
ns
—
ns
—
ns
—
ns
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