XP2 Datasheet, PDF (29/92 Pages) Lattice Semiconductor – LatticeXP2 Family Data Sheet

Lattice Semiconductor
Architecture
LatticeXP2 Family Data Sheet
Programmable I/O Cells (PIC)
Each PIC contains two PIOs connected to their respective sysIO buffers as shown in Figure 2-25. The PIO Block
supplies the output data (DO) and the tri-state control signal (TO) to the sysIO buffer and receives input from the
buffer. Table 2-11 provides the PIO signal list.
Figure 2-25. PIC Diagram
TD
OPOS1
ONEG1
PIOA
IOLT0
Tristate
Register
Block
OPOS0
OPOS2¹
ONEG0
ONEG2¹
IOLD0
Output
Register
Block
PADA
“T”
sysIO
Buffer
QNEG0¹
QNEG1¹
QPOS0¹
QPOS1¹
INCK²
INDD
INFF
IPOS0
IPOS1
CLK
CE
LSR
GSRN
ECLK1
ECLK2
DDRCLKPOL¹
DQSXFER¹
DQS
DEL
Control
Muxes
CLK1
CEO
LSR
GSR
CLK0
CEI
DI
Input
Register
Block
PIOB
PADB
“C”
1. Signals are available on left/right/bottom edges only.
2. Selected blocks.
Two adjacent PIOs can be joined to provide a differential I/O pair (labeled as “T” and “C”) as shown in Figure 2-25.
The PAD Labels “T” and “C” distinguish the two PIOs. Approximately 50% of the PIO pairs on the left and right
edges of the device can be configured as true LVDS outputs. All I/O pairs can operate as inputs.
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