XP2 Datasheet, PDF (10/92 Pages) Lattice Semiconductor – LatticeXP2 Family Data Sheet

Lattice Semiconductor
Figure 2-4. General Purpose PLL (GPLL) Diagram
WRDEL
DDUTY
DPHASE
CLKI
CLKFB
RSTK
RST
CLKI
Divider
CLKFB
Divider
PFD
VCO/
LOOP FILTER
Internal Feedback
Architecture
LatticeXP2 Family Data Sheet
CLKOP
Divider
Phase/
Duty Cycle/
Duty Trim
Duty Trim
CLKOK
Divider
Lock
Detect
CLKOK2
3
CLKOS
CLKOP
CLKOK
LOCK
Table 2-4 provides a description of the signals in the GPLL blocks.
Table 2-4. GPLL Block Signal Descriptions
Signal
CLKI
CLKFB
RST
RSTK
DPHASE [3:0]
DDDUTY [3:0]
WRDEL
CLKOS
CLKOP
CLKOK
CLKOK2
LOCK
I/O
Description
I Clock input from external pin or routing
I
PLL feedback input from CLKOP (PLL internal), from clock net (CLKOP) or from a user clock
(PIN or logic)
I “1” to reset PLL counters, VCO, charge pumps and M-dividers
I “1” to reset K-divider
I DPA Phase Adjust input
I DPA Duty Cycle Select input
I DPA Fine Delay Adjust input
O PLL output clock to clock tree (phase shifted/duty cycle changed)
O PLL output clock to clock tree (no phase shift)
O PLL output to clock tree through secondary clock divider
O PLL output to clock tree (CLKOP divided by 3)
O “1” indicates PLL LOCK to CLKI
Clock Dividers
LatticeXP2 devices have two clock dividers, one on the left side and one on the right side of the device. These are
intended to generate a slower-speed system clock from a high-speed edge clock. The block operates in a ÷2, ÷4 or
÷8 mode and maintains a known phase relationship between the divided down clock and the high-speed clock
based on the release of its reset signal. The clock dividers can be fed from the CLKOP output from the GPLLs or
from the Edge Clocks (ECLK). The clock divider outputs serve as primary clock sources and feed into the clock dis-
tribution network. The Reset (RST) control signal resets the input and forces all outputs to low. The RELEASE sig-
nal releases outputs to the input clock. For further information on clock dividers, please see TN1126, sysCLOCK
PLL Design and Usage Guide. Figure 2-5 shows the clock divider connections.
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