XP2 Datasheet, PDF (66/92 Pages) Lattice Semiconductor – LatticeXP2 Family Data Sheet

Lattice Semiconductor
EBR Timing Diagrams
Figure 3-6. Read/Write Mode (Normal)
CLKA
DC and Switching Characteristics
LatticeXP2 Family Data Sheet
CSA
WEA
ADA
DIA
DOA
A0
A1
tSU tH
D0
D1
Invalid Data
A0
A1
A0
tCO_EBR
t_{CO_EBR}
D0
tCO_EBR
D1
D0
Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock.
Figure 3-7. Read/Write Mode with Input and Output Registers
CLKA
CSA
WEA
ADA
DIA
DOA (Regs)
A0
A1
A0
A1
tSU tH
D0
D1
tCOO_EBR
Mem(n) data from previous read
output is only updated during a read cycle
A0
tCOO_EBR
D0
D1
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