XP2 Datasheet, PDF (65/92 Pages) Lattice Semiconductor – LatticeXP2 Family Data Sheet

Lattice Semiconductor
DC and Switching Characteristics
LatticeXP2 Family Data Sheet
LatticeXP2 Internal Switching Characteristics¹ (Continued)
Over Recommended Operating Conditions
-7
Parameter
Description
Min.
Max.
t_{HP_DSP}
t_{SUO_DSP}
t_{HO_DSP}
t_{COI_DSP}³
Pipeline Register Hold Time
Output Register Setup Time
Output Register Hold Time
Input Register Clock to Output
Time
-0.787
4.896
-1.439
—
—
—
—
4.513
t_{COP_DSP}³
Pipeline Register Clock to Output
Time
—
2.153
t_{COO_DSP}³
Output Register Clock to Output
Time
—
0.569
t_SUADSUB
AdSub Input Register Setup Time -0.270
—
t_HADSUB
AdSub Input Register Hold Time 0.306
—
1. Internal parameters are characterized, but not tested on every device.
2. RST resets VCO and all counters in PLL.
3. These parameters include the Adder Subtractor block in the path.
Timing v. A 0.12
-6
Min.
Max.
-0.890
—
5.413
—
-1.604
—
—
4.947
—
2.272
—
-0.298
0.338
0.600
—
—
-5
Min.
Max.
-0.994
—
5.931
—
-1.770
—
—
5.382
—
2.391
—
-0.327
0.371
0.631
—
—
Units
ns
ns
ns
ns
ns
ns
ns
ns
3-21