XP2 Datasheet, PDF (27/92 Pages) Lattice Semiconductor – LatticeXP2 Family Data Sheet

Lattice Semiconductor
Architecture
LatticeXP2 Family Data Sheet
register. Similarly, CE and RST are selected from their four respective sources (CE0, CE1, CE2, CE3 and RST0,
RST1, RST2, RST3) at each input register, pipeline register and output register.
Signed and Unsigned with Different Widths
The DSP block supports other widths, in addition to x9, x18 and x36 widths, of signed and unsigned multipliers. For
unsigned operands, unused upper data bits should be filled to create a valid x9, x18 or x36 operand. For signed
two’s complement operands, sign extension of the most significant bit should be performed until x9, x18 or x36
width is reached. Table 2-7 provides an example of this.
Table 2-7. Sign Extension Example
Number
+5
-6
Unsigned
0101
N/A
Unsigned
9-bit
000000101
N/A
Unsigned
18-bit
000000000000000101
N/A
Signed
0101
1010
Two’s Complement
Signed 9 Bits
000000101
111111010
Two’s Complement
Signed 18 Bits
000000000000000101
111111111111111010
OVERFLOW Flag from MAC
The sysDSP block provides an overflow output to indicate that the accumulator has overflowed. “Roll-over” occurs
and an overflow signal is indicated when any of the following is true: two unsigned numbers are added and the
result is a smaller number than the accumulator, two positive numbers are added with a negative sum or two nega-
tive numbers are added with a positive sum. Note that when overflow occurs the overflow flag is present for only
one cycle. By counting these overflow pulses in FPGA logic, larger accumulators can be constructed. The condi-
tions for the overflow signal for signed and unsigned operands are listed in Figure 2-24.
Figure 2-24. Accumulator Overflow/Underflow
011111100 252
011111101 ²⁵³
011111110 ²⁵⁴
011111111 ²⁵⁵
100000000 ²⁵⁶
100000001 ²⁵⁷
100000010 ²⁵⁸
000000011
000000010
000000001
000000000
3
2
1
0
Carry signal is generated for
one cycle when this
boundary is crossed
111111111 511
111111110 510
111111101 509
Unsigned Operation
Overflow signal is generated
for one cycle when this
boundary is crossed
011111100
011111101
011111110
011111111
100000000
100000001
100000010
252
253
254
255
-256
-255
-254
000000011 +3
000000010 +2
000000001 +1
000000000 0
111111111 ^-1
111111110 ^-2
111111101 ^-3
Signed Operation
2-24