XP2 Datasheet, PDF (5/92 Pages) Lattice Semiconductor – LatticeXP2 Family Data Sheet

Lattice Semiconductor
Architecture
LatticeXP2 Family Data Sheet
Figure 2-1. Simplified Block Diagram, LatticeXP2-17 Device (Top Level)
sysIO Buffers,
Pre-Engineered Source
Synchronous Support
On-chip
Oscillator
Programmable
Function Units
(PFUs)
SPI Port
sysMEM Block
RAM
DSP Blocks
JTAG Port
Flash
sysCLOCK PLLs
Flexible Routing
PFU Blocks
The core of the LatticeXP2 device is made up of logic blocks in two forms, PFUs and PFFs. PFUs can be pro-
grammed to perform logic, arithmetic, distributed RAM and distributed ROM functions. PFF blocks can be pro-
grammed to perform logic, arithmetic and ROM functions. Except where necessary, the remainder of this data
sheet will use the term PFU to refer to both PFU and PFF blocks.
Each PFU block consists of four interconnected slices, numbered Slice 0 through Slice 3, as shown in Figure 2-2.
All the interconnections to and from PFU blocks are from routing. There are 50 inputs and 23 outputs associated
with each PFU block.
2-2