XP2 Datasheet, PDF (36/92 Pages) Lattice Semiconductor – LatticeXP2 Family Data Sheet

Lattice Semiconductor
Figure 2-31. DQS Local Bus
Architecture
LatticeXP2 Family Data Sheet
DQSXFER
DQS
DQS
DCNTL[6:0]
ECLK1
DQSXFER
DCNTL[6:0]
GSR
CEI
CLK1
DQS
PIO
Output
Register Block
Input
Register Block
To Sync
Reg.
To DDR
Reg.
PIO
Polarity Control
Logic
DQSDEL
Calibration bus
from DLL
DQSXFERDEL*
sysIO
Buffer
DDR
Datain
PAD
DI
sysIO
Buffer
DQS
Strobe
PAD
DI
*DQSXFERDEL shifts ECLK1 by 90% and is not associated with a particular PIO.
Polarity Control Logic
In a typical DDR memory interface design, the phase relationship between the incoming delayed DQS strobe and
the internal system clock (during the READ cycle) is unknown. The LatticeXP2 family contains dedicated circuits to
transfer data between these domains. To prevent set-up and hold violations, at the domain transfer between DQS
(delayed) and the system clock, a clock polarity selector is used. This changes the edge on which the data is regis-
tered in the synchronizing registers in the input register block and requires evaluation at the start of each READ
cycle for the correct clock polarity.
Prior to the READ operation in DDR memories, DQS is in tristate (pulled by termination). The DDR memory device
drives DQS low at the start of the preamble state. A dedicated circuit detects this transition. This signal is used to
control the polarity of the clock to the synchronizing registers.
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