XP2 Datasheet, PDF (37/92 Pages) Lattice Semiconductor – LatticeXP2 Family Data Sheet

Lattice Semiconductor
Architecture
LatticeXP2 Family Data Sheet
DQSXFER
LatticeXP2 devices provide a DQSXFER signal to the output buffer to assist it in data transfer to DDR memories
that require DQS strobe be shifted 90^o. This shifted DQS strobe is generated by the DQSDEL block. The
DQSXFER signal runs the span of the data bus.
sysIO Buffer
Each I/O is associated with a flexible buffer referred to as a sysIO buffer. These buffers are arranged around the
periphery of the device in groups referred to as banks. The sysIO buffers allow users to implement the wide variety
of standards that are found in today’s systems including LVCMOS, SSTL, HSTL, LVDS and LVPECL.
sysIO Buffer Banks
LatticeXP2 devices have eight sysIO buffer banks for user I/Os arranged two per side. Each bank is capable of sup-
porting multiple I/O standards. Each sysIO bank has its own I/O supply voltage (V_CCIO). In addition, each bank has
voltage references, V_REF1 and V_REF2, that allow it to be completely independent from the others. Figure 2-32
shows the eight banks and their associated supplies.
In LatticeXP2 devices, single-ended output buffers and ratioed input buffers (LVTTL, LVCMOS and PCI) are pow-
ered using V_CCIO. LVTTL, LVCMOS33, LVCMOS25 and LVCMOS12 can also be set as fixed threshold inputs inde-
pendent of V_CCIO.
Each bank can support up to two separate V_REF voltages, V_REF1 and V_REF2, that set the threshold for the refer-
enced input buffers. Some dedicated I/O pins in a bank can be configured to be a reference voltage supply pin.
Each I/O is individually configurable based on the bank’s supply and reference voltages.
Figure 2-32. LatticeXP2 Banks
TOP
V _CCIO7
V _REF1(7)
V _REF2(7)
GND
V _CCIO6
V _REF1(6)
V _REF2(6)
GND
Bank 0
Bank 1
Bank 5
Bank 4
V _CCIO2
V _REF1(2)
V _REF2(2)
GND
V _CCIO3
V _REF1(3)
V _REF2(3)
GND
BOTTOM
2-34