XP2 Datasheet, PDF (16/92 Pages) Lattice Semiconductor – LatticeXP2 Family Data Sheet

Lattice Semiconductor
Architecture
LatticeXP2 Family Data Sheet
LatticeXP2-30 and smaller devices have six secondary clock regions. All devices in the LatticeXP2 family have four
secondary clocks (SC0 to SC3) which are distributed to every region.
The secondary clock muxes are located in the center of the device. Figure 2-12 shows the mux structure of the
secondary clock routing. Secondary clocks SC0 to SC3 are used for clock and control and SC4 to SC7 are used for
high fan-out signals.
Figure 2-11. Secondary Clock Regions XP2-40
I/O Bank 0
Secondary Clock
Region 1
I/O Bank 1
Secondary Clock
Region 5
Vertical Routing
Channel Regional
Boundary
EBR Row
Regional
Boundary
Secondary Clock
Region 2
Secondary Clock
Region 6
Secondary Clock
Region 3
Secondary Clock
Region 4
I/O Bank 5
Secondary Clock
Region 7
Secondary Clock
Region 8
I/O Bank 4
EBR Row
Regional
Boundary
DSP Row
Regional
Boundary
2-13