XP2 Datasheet, PDF (18/92 Pages) Lattice Semiconductor – LatticeXP2 Family Data Sheet

Lattice Semiconductor
Figure 2-14. Slice0 through Slice2 Control Selection
Architecture
LatticeXP2 Family Data Sheet
Secondary Clock
3
Routing
12
Vcc
1
16:1
Slice Control
Edge Clock Routing
LatticeXP2 devices have eight high-speed edge clocks that are intended for use with the PIOs in the implementa-
tion of high-speed interfaces. Each device has two edge clocks per edge. Figure 2-15 shows the selection muxes
for these clocks.
Figure 2-15. Edge Clock Mux Connections
Clock Input Pad
Top and Bottom
Edge Clocks
ECLK1/ ECLK2
Routing
(Both Muxes)
Input Pad
GPLL Input Pad
GPLL Output CLKOP
Routing
Left and Right
Edge Clocks
ECLK1
Input Pad
GPLL Input Pad
GPLL Output CLKOS
Routing
Left and Right
Edge Clocks
ECLK2
2-15