XP2 Datasheet, PDF (11/92 Pages) Lattice Semiconductor – LatticeXP2 Family Data Sheet

Lattice Semiconductor
Figure 2-5. Clock Divider Connections
Architecture
LatticeXP2 Family Data Sheet
ECLK
÷1
CLKOP (GPLL)
÷2
CLKDIV
÷4
RST
RELEASE
÷8
Clock Distribution Network
LatticeXP2 devices have eight quadrant-based primary clocks and between six and eight flexible region-based sec-
ondary clocks/control signals. Two high performance edge clocks are available on each edge of the device to sup-
port high speed interfaces. The clock inputs are selected from external I/Os, the sysCLOCK PLLs, or routing. Clock
inputs are fed throughout the chip via the primary, secondary and edge clock networks.
Primary Clock Sources
LatticeXP2 devices derive primary clocks from four sources: PLL outputs, CLKDIV outputs, dedicated clock inputs
and routing. LatticeXP2 devices have two to four sysCLOCK PLLs, located in the four corners of the device. There
are eight dedicated clock inputs, two on each side of the device. Figure 2-6 shows the primary clock sources.
2-8