XP2 Datasheet, PDF (62/92 Pages) Lattice Semiconductor – LatticeXP2 Family Data Sheet

Lattice Semiconductor
DC and Switching Characteristics
LatticeXP2 Family Data Sheet
LatticeXP2 External Switching Characteristics (Continued)
Over Recommended Operating Conditions
Parameter
Description
Device
XP2-5
t_{H_DELPLL}
Clock to Data Hold - PIO Input
Register with Input Data Delay
XP2-8
XP2-17
XP2-30
XP2-40
DDR² and DDR2³ I/O Pin Parameters
t_DVADQ
Data Valid After DQS
(DDR Read)
XP2
t_DVEDQ
Data Hold After DQS
(DDR Read)
XP2
t_DQVBS
Data Valid Before DQS
t_DQVAS
Data Valid After DQS
f_{MAX_DDR}
DDR Clock Frequency
f_{MAX_DDR2}
DDR Clock Frequency
Primary Clock
XP2
XP2
XP2
XP2
f_{MAX_PRI}
t_{W_PRI}
Frequency for Primary Clock Tree XP2
Clock Pulse Width for Primary
Clock
XP2
t_{SKEW_PRI}
Primary Clock Skew Within a
Bank
XP2
Edge Clock (ECLK1 and ECLK2)
f_{MAX_ECLK}
t_{W_ECLK}
Frequency for Edge Clock
Clock Pulse Width for Edge
Clock
XP2
XP2
t_{SKEW_ECLK}
Edge Clock Skew Within an Edge
of the Device
XP2
1. General timing numbers based on LVCMOS 2.5, 12mA, 0pf load.
2. DDR timing numbers based on SSTL25.
3. DDR2 timing numbers based on SSTL18.
Timing v. A 0.12
-7
Min. Max.
0.00 —
0.00 —
0.00 —
0.00 —
0.00 —
— 0.29
0.71 —
0.25 —
0.25 —
95
200
133 200
—
420
1
—
—
160
—
420
1
—
—
130
-6
Min. Max.
0.00 —
0.00 —
0.00 —
0.00 —
0.00 —
— 0.29
0.71 —
0.25 —
0.25 —
95
166
133 200
—
357
1
—
—
160
—
357
1
—
—
130
-5
Min. Max.
0.00 —
0.00 —
0.00 —
0.00 —
0.00 —
Units
ns
ns
ns
ns
ns
— 0.29 UI
0.71 —
UI
0.25 —
UI
0.25 —
UI
95
133 MHz
133 166 MHz
—
311 MHz
1
—
ns
—
160
ps
—
311 MHz
1
—
ns
—
130
ps
3-18