XP2 Datasheet, PDF (79/92 Pages) Lattice Semiconductor – LatticeXP2 Family Data Sheet

Lattice Semiconductor
Pinout Information
LatticeXP2 Family Data Sheet
Signal Descriptions (Cont.)
Signal Name
I/O
Description
TDO
O Output pin. Test Data Out pin used to shift data out of a device using 1149.1.
VCCJ
— Power supply pin for JTAG Test Access Port.
Configuration Pads (Used during sysCONFIG)
CFG[1:0]
I
Mode pins used to specify configuration mode values latched on rising edge
of INITN. During configuration, an internal pull-up is enabled.
INITN¹
I/O
Open Drain pin. Indicates the FPGA is ready to be configured. During config-
uration, a pull-up is enabled.
PROGRAMN
I
Initiates configuration sequence when asserted low. This pin always has an
active pull-up.
DONE
I/O
Open Drain pin. Indicates that the configuration sequence is complete, and
the startup sequence is in progress.
CCLK
I/O Configuration Clock for configuring an FPGA in sysCONFIG mode.
SISPI²
I/O Input data pin in slave SPI mode and Output data pin in Master SPI mode.
SOSPI²
I/O Output data pin in slave SPI mode and Input data pin in Master SPI mode.
CSSPIN²
O
Chip select for external SPI Flash memory in Master SPI mode. This pin has
a weak internal pull-up.
CSSPISN
I Chip select in Slave SPI mode. This pin has a weak internal pull-up.
TOE
Test Output Enable tristates all I/O pins when driven low. This pin has a weak
I internal pull-up, but when not used an external pull-up to V_CC is recom-
mended.
1. If not actively driven, the internal pull-up may not be sufficient. An external pull-up resistor of 4.7k to 10k ohms is recommended.
2. When using the device in Master SPI mode, it must be mutually exclusive from JTAG operations (i.e. TCK tied to GND) or the JTAG TCK
must be free-running when used in a system JTAG test environment. If Master SPI mode is used in conjunction with a JTAG download
cable, the device power cycle is required after the cable is unplugged.
4-2