XP2 Datasheet, PDF (77/92 Pages) Lattice Semiconductor – LatticeXP2 Family Data Sheet

Lattice Semiconductor
DC and Switching Characteristics
LatticeXP2 Family Data Sheet
Switching Test Conditions
Figure 3-11 shows the output test load that is used for AC testing. The specific values for resistance, capacitance,
voltage, and other test conditions are shown in Table 3-6.
Figure 3-11. Output Test Load, LVTTL and LVCMOS Standards
V_T
DUT
R1
Test Poi nt
R2
CL*
*CL Includes Test Fixture and Probe Capacitance
Table 3-6. Test Fixture Required Components, Non-Terminated Interfaces
Test Condition
R₁
R₂
C_L
Timing Ref.
LVCMOS 3.3 = 1.5V
LVCMOS 2.5 = V_CCIO/2
LVTTL and other LVCMOS settings (L -> H, H -> L)
∞
∞
0pF LVCMOS 1.8 = V_CCIO/2
LVCMOS 1.5 = V_CCIO/2
LVCMOS 2.5 I/O (Z -> H)
LVCMOS 2.5 I/O (Z -> L)
LVCMOS 2.5 I/O (H -> Z)
LVCMOS 2.5 I/O (L -> Z)
∞
1MΩ
∞
100
1MΩ
∞
100
∞
LVCMOS 1.2 = V_CCIO/2
V_CCIO/2
V_CCIO/2
V_OH - 0.10
V_OL + 0.10
Note: Output test conditions for all other interfaces are determined by the respective standards.
V_T
—
—
—
—
—
—
V_CCIO
—
V_CCIO
3-33