XP2 Datasheet, PDF (32/92 Pages) Lattice Semiconductor – LatticeXP2 Family Data Sheet

Lattice Semiconductor
Architecture
LatticeXP2 Family Data Sheet
shows the diagram using this gearbox function. For more information on this topic, see TN1138, LatticeXP2 High
Speed I/O Interface.
Figure 2-27. Output and Tristate Block
TD
ONEG1
OPOS1
Tristate Logic
D
Q
D-Type
/LATCH
D
Q
D-Type
D
Q
Latch
0
1
0
TO
1
0
1
ONEG0
OPOS0
CLKA
ECLK1
ECLK2
CLK1
(CLKA)
DQSXFER
DQ
D-Type*
DQ
D-Type*
Clock Transfer
Registers
DQ
0
Latch
1
0
0
1
1
0
1
0
1
0
1
TD
ONEG1
Tristate Logic
OPOS1
D
Q
D-Type
/LATCH
D
Q
D-Type
DDR Output
Registers
DO
0
D
Q
1
0
1
Latch
Programmable
Control
Output Logic
True PIO (A) in LVDS I/O Pair
Comp PIO (B) in LVDS I/O Pair
D
Q
D-Type
/LATCH
D
Q
D-Type
D
Q
Latch
0
1
0
TO
1
0
1
ONEG0
OPOS0
D
Q
D-Type*
D
Q
D-Type*
DQ
Latch
CLKB
ECLK1
ECLK2
CLK1
(CLKB)
DQSXFER
Clock Transfer
Registers
* Shared with input register
D
Q
D-Type
/LATCH
D
Q
D-Type
DDR Output
Registers
DO
0
1
0
D
Q
1
Latch
0
1
0
1
Programmable
Control
Output Logic
Note: Simplified version does not show CE and SET/RESET details
2-29