XP2 Datasheet, PDF (7/92 Pages) Lattice Semiconductor – LatticeXP2 Family Data Sheet

Lattice Semiconductor
Figure 2-3. Slice Diagram
FXB
FXA
A1
B1
C1
D1
M1
M0
From
Routing
A0
B0
C0
D0
Architecture
LatticeXP2 Family Data Sheet
FCO from Slice/PFU, FCI into Different Slice/PFU
CO
F/SUM
LUT4 &
CARRY*
CI
LUT5
Mux
CO
LUT4 &
CARRY* _F/SUM
CI
SLICE
D
FF*
OFX1
F1
Q1
To
Routing
OFX0
F0
D
Q0
FF*
CE
CLK
LSR
* Not in Slice 3
FCI into Slice/PFU, FCO from Different Slice/PFU
For Slices 0 and 2, memory control signals are generated from Slice 1 as follows:
WCK is CLK
WRE is from LSR
DI[3:2] for Slice 2 and DI[1:0] for Slice 0 data
WAD [A:D] is a 4bit address from slice 1 LUT input
Table 2-2. Slice Signal Descriptions
Function
Type
Signal Names
Input
Data signal
A0, B0, C0, D0
Input
Data signal
A1, B1, C1, D1
Input
Multi-purpose
M0
Input
Multi-purpose
M1
Input
Control signal
CE
Input
Control signal
LSR
Input
Control signal
CLK
Input Inter-PFU signal
FCI
Input Inter-slice signal
FXA
Input Inter-slice signal
FXB
Output
Data signals
F0, F1
Output
Data signals
Q0, Q1
Output
Data signals
OFX0
Output
Data signals
OFX1
Output Inter-PFU signal
FCO
1. See Figure 2-3 for connection details.
2. Requires two PFUs.
Description
Inputs to LUT4
Inputs to LUT4
Multipurpose Input
Multipurpose Input
Clock Enable
Local Set/Reset
System Clock
Fast Carry-In¹
Intermediate signal to generate LUT6 and LUT7
Intermediate signal to generate LUT6 and LUT7
LUT4 output register bypass signals
Register outputs
Output of a LUT5 MUX
Output of a LUT6, LUT7, LUT8² MUX depending on the slice
Slice 2 of each PFU is the fast carry chain output¹
2-4