XP2 Datasheet, PDF (81/92 Pages) Lattice Semiconductor – LatticeXP2 Family Data Sheet

Lattice Semiconductor
Pinout Information
LatticeXP2 Family Data Sheet
Pin Information Summary
XP2-5
XP2-8
XP2-17
XP2-30
XP2-40
Pin Type
132 144 208 256 132 144 208 256 208 256 484 256 484 672 484 672
csBGA TQFP PQFP ftBGA csBGA TQFP PQFP ftBGA PQFP ftBGA fpBGA ftBGA fpBGA fpBGA fpBGA fpBGA
Single Ended User I/O
86 100 146 172 86 100 146 201 146 201 358 201 363 472 363 540
Differential Pair ^Normal
35
39 57 66
35
39 57 77 57 77 135 77 137 180 137 204
User I/O
Highspeed 8
11 16 20
8
11 16 23 16 23
44
23
44
56
44
66
TAP
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
Configuration Muxed
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
Dedicated 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Non Configura- ^Muxed
5
5
7
7
7
7
9
9
11 11
21
7
11
13
11
13
tion
Dedicated 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Vcc
6
4
9
6
6
4
9
6
9
6
16
6
16
20
16
20
Vccaux
4
4
4
4
4
4
4
4
4
4
8
4
8
8
8
8
VCCPLL
2
2
2
-
2
2
2
-
4
-
-
-
-
-
-
-
Bank0
2
2
2
2
2
2
2
2
2
2
4
2
4
4
4
4
Bank1
1
1
2
2
1
1
2
2
2
2
4
2
4
4
4
4
Bank2
2
2
2
2
2
2
2
2
2
2
4
2
4
4
4
4
VCCIO
Bank3
Bank4
1
1
2
2
1
1
2
2
2
2
4
2
4
4
4
4
1
1
2
2
1
1
2
2
2
2
4
2
4
4
4
4
Bank5
2
2
2
2
2
2
2
2
2
2
4
2
4
4
4
4
Bank6
1
1
2
2
1
1
2
2
2
2
4
2
4
4
4
4
Bank7
2
2
2
2
2
2
2
2
2
2
4
2
4
4
4
4
GND, GND0-GND7
15 15 20 20
15 15 22 20 22 20
56
20
56
64
56
64
NC
-
-
4
31
-
-
2
2
-
2
7
2
2
69
2
1
Bank0
18/9 20/10 20/10 26/13 18/9 20/10 20/10 28/14 20/10 28/14 52/26 28/14 52/26 70/35 52/26 70/35
Bank1
4/2 6/3 18/9 18/9 4/2 6/3 18/9 22/11 18/9 22/11 36/18 22/11 36/18 54/27 36/18 70/35
Bank2
16/8 18/9 18/9 22/11 16/8 18/9 18/9 26/13 18/9 26/13 46/23 26/13 46/23 56/28 46/23 64/32
Single Ended/
Differential I/O
per Bank
Bank3
Bank4
4/2 4/2 16/8 20/10 4/2 4/2 16/8 24/12 16/8 24/12 44/22 24/12 46/23 56/28 46/23 66/33
8/4 8/4 18/9 18/9 8/4 8/4 18/9 26/13 18/9 26/13 36/18 26/13 38/19 54/27 38/19 70/35
Bank5
14/7 18/9 20/10 24/12 14/7 18/9 20/10 24/12 20/10 24/12 52/26 24/12 53/26 70/35 53/26 70/35
Bank6
6/3 8/4 18/9 22/11 6/3 8/4 18/9 27/13 18/9 27/13 46/23 27/13 46/23 56/28 46/23 66/33
Bank7
16/8 18/9 18/9 22/11 16/8 18/9 18/9 24/12 18/9 24/12 46/23 24/12 46/23 56/28 46/23 64/32
Bank0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank2
3
4
4
5
3
4
4
6
4
6
11
6
11
14
11
16
True LVDS Pairs _Bank3
Bonding Out per
Bank
Bank4
1
1
4
5
1
1
4
6
4
6
11
6
11
14
11
17
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank6
1
2
4
5
1
2
4
6
4
6
11
6
11
14
11
17
Bank7
3
4
4
5
3
4
4
5
4
5
11
5
11
14
11
16
Bank0
1
1
1
1
1
1
1
1
1
1
3
1
2
4
2
4
Bank1
0
0
1
1
0
0
1
1
1
1
2
1
2
3
2
4
Bank2
1
1
1
1
1
1
1
1
1
1
2
1
3
3
3
4
DDR Banks
Bank3
Bonding Out per
I/O Bank¹
Bank4
0
0
1
1
0
0
1
1
1
1
2
1
3
3
3
4
0
0
1
1
0
0
1
1
1
1
2
1
2
3
2
4
Bank5
1
1
1
1
1
1
1
1
1
1
3
1
2
4
2
4
Bank6
0
0
1
1
0
0
1
1
1
1
2
1
3
3
3
4
Bank7
1
1
1
1
1
1
1
1
1
1
2
1
3
3
3
4
4-4