XP2 Datasheet, PDF (59/92 Pages) Lattice Semiconductor – LatticeXP2 Family Data Sheet

Lattice Semiconductor
DC and Switching Characteristics
LatticeXP2 Family Data Sheet
Register-to-Register Performance (Continued)
Function
-7 Timing
Units
DSP IP Functions
16-Tap Fully-Parallel FIR Filter
198
MHz
1024-pt FFT
221
MHz
8X8 Matrix Multiplication
196
MHz
1. These timing numbers were generated using the ispLEVER design tool. Exact performance may vary with device, design and tool version.
The tool uses internal parameters that have been characterized but are not tested on every device.
Timing v. A 0.12
Derating Timing Tables
Logic timing provided in the following sections of this data sheet and the ispLEVER design tools are worst case
numbers in the operating range. Actual delays at nominal temperature and voltage for best case process, can be
much better than the values given in the tables. The ispLEVER design tool can provide logic timing numbers at a
particular temperature and voltage.
3-15