XP2 Datasheet, PDF (34/92 Pages) Lattice Semiconductor – LatticeXP2 Family Data Sheet

Lattice Semiconductor
Figure 2-28. DQS Input Routing (Left and Right)
DQS
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
Figure 2-29. DQS Input Routing (Top and Bottom)
DQS
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
Architecture
LatticeXP2 Family Data Sheet
sysIO
Buffer
Delay
PADA "T"
LVDS Pair
PADB "C"
PADA "T"
LVDS Pair
PADB "C"
PADA "T"
LVDS Pair
PADB "C"
PADA "T"
LVDS Pair
PADB "C"
Assigned
DQS Pin
PADA "T"
LVDS Pair
PADB "C"
PADA "T"
LVDS Pair
PADB "C"
PADA "T"
LVDS Pair
PADB "C"
PADA "T"
LVDS Pair
PADB "C"
sysIO
Buffer
Delay
PADA "T"
LVDS Pair
PADB "C"
PADA "T"
LVDS Pair
PADB "C"
PADA "T"
LVDS Pair
PADB "C"
PADA "T"
LVDS Pair
PADB "C"
Assigned
DQS Pin
PADA "T"
LVDS Pair
PADB "C"
PADA "T"
LVDS Pair
PADB "C"
PADA "T"
LVDS Pair
PADB "C"
PADA "T"
LVDS Pair
PADB "C"
PADA "T"
LVDS Pair
PADB "C"
2-31